11.4 A Double Step-Down Dual-Output Converter with Cross Regulation of 0.025mV/mA and Improved Current Balance

Based on the Power Delivery (PD) 3.1 standard, the voltage conversion from 48V input system becomes important for today's electronics. Due to the usage of high voltage switches, the need for small font factor and multiple outputs for high power density power management becomes imperative in Internet-of-Things (loT) electronics. Thus, single-inductor dual-output (SIDO) converters (top left of Fig. 11.4.1) become one of the best candidates due to its dual outputs with the use of a single inductor [1]-[3]. However, the bulky inductor determined by the maximum current driving capability is not efficient at light loads. In addition, SIDO converters also suffer from large output voltage ripple due to its discontinuous energy deliver to the outputs. The double step down (DSD) converter, with two small inductors and one flying capacitor, not only reduces the voltage stress of each component but also increases power density (top right of Fig. 11.4.1) [4]-[6]. However, if dual outputs are required, double components are required. To take advantages of SIDO and DSD converters, this paper presents the DSD dual-output (DSD-DO) converter for loT electronics (bottom left of Fig. 11.4.1). This converter only requires one 48V device and three 24V devices, while the rest of the switches are 5V devices. In the main energy transfer path (bottom right of Fig. 11.4.1), two small inductors L1 and L2 supply energy to VOA and VOB, respectively, through operation Path 1, and to VOB and VOA, respectively, through operation Path 2. Since both VOA and VOB can draw energy from VIN during majority of the switching cycle, the output voltage ripple can be effectively reduced in steady state. Each inductor current of the DSD-DO is half of that in the SIDO [1]-[3], which reduces conduction loss and output voltage ripple (Delta VOA(B)). Conventional DSD [5] has a serious problem with inductor current imbalance from different inductor current slopes. That is, mL1,textup for L1 is greater than mL2,textup for L2 due to an extra switch in the flying capacitor CF discharge loop, resulting in uneven voltage ripple and potential hot spot issues. Through the proposed timing balance mechanism (TBM), the duration of Path 1 and Path 2 can be adjusted according to the output load currents IOA and IOB, which balances the two inductor currents. Therefore, low output voltage ripple can be guaranteed at both outputs. To further alleviate the cross-regulation problem in SIDO when the load changes from light to heavy, the Hybrid Sum and Deviation (HSD) technique is presented. This technique controls the auxiliary energy transfer path, which can boost the droop voltages of VOA and VOB to their regulation voltages via Path 3 and Path 4, respectively (bottom right corner of Fig. 11.4.1).