1100 V, 22.9 mΩcm²4H-SiC RESURF Lateral Double-Implanted MOSFET with Trench Isolation

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device Lch = 0.8 μm and Ld = 12 μm shows an RON,sp of 22.9 mΩ cm2 at a VGS of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/RON,sp of 55.5 MW/cm2. Devices that have different Lch, LJFET, Ld, and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The RON × QG and RON × QGD values are calculated as 17.7 and 9.0 Ω nC, respectively, which are promising for power-integrated circuit applications.