@inproceedings{cfbeda806c914371b2272e48dc1d0b05,
title = "10-bit SAR ADC with novel pseudo-random capacitor switching scheme",
abstract = "This paper presents a pseudo-random capacitor switching scheme. Taking 1\% of capacitor mismatch into account, after applying the pseudo-random switching scheme to the SAR ADC matlab behavioral model, for 500 Monte Carlo simulations, the missing code (Minimum DNL=-1) occurrence is reduced from 176 to 3, and the other performance indicators are also improved significantly. The circuit was fabricated by using 0.18-μm 1P6M TSMC CMOS process. With a sampling rate of 1KS/s and 50Hz input frequency, the measured SNDR and SFDR achieves 57.11dB and 75.37dB respectively while consuming a power of 7.68μW. With a sampling rate of 48KS/s and 500Hz input frequency, the measured SNDR and SFDR achieves 56.91dB and 74.47dB respectively while consuming a power of 7.93μW. With a sampling rate of 1MS/s and 50KHz input frequency, the measured SNDR and SFDR achieves 58.71dB and 77.89dB respectively while consuming a power of 102μW. The measured INL is 0.54/-0.78 LSB, and DNL is 0.67/-0.82 LSB. The circuit is applicable for various bio-medical applications.",
keywords = "High-performance, Low power, Pseudo-random, Successive-approximation-register analog-to-digital converter",
author = "Hsu, \{Pai Hsiang\} and Lee, \{Yueh Ru\} and Hung, \{Chung Chih\}",
year = "2019",
month = apr,
doi = "10.1109/VLSI-DAT.2019.8741534",
language = "English",
series = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019",
address = "美國",
note = "2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 ; Conference date: 22-04-2019 Through 25-04-2019",
}