10 bit 40 MHz ADC using 0.8 μm Bi-CMOS technology

Kazunori Tsugaru*, Yasuhiro Sugimoto, Makoto Noda, Hiroshi Iwai, Gen Sasaki, Yoshio Suwa

*此作品的通信作者

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

A 10-b analog-to-digital converter applicable to digital video equipment and using 0.8-μm BiCMOS technology is discussed. In order to reduce power dissipation and chip size, a two-step parallel type conversion scheme is utilized. The 10-bit resolution has been realized at a maximum conversion rate of 40 MHz, power dissipation of 700 mW, and chip size of 4.1- × 4.8-mm2. A scheme that transforms coarse reference voltages to fine ladder resistors using buffer amplifiers has been used. As the emitter follower circuit can be used for the buffer amplifier, a small setling time is obtained. A subranging architecture has been adopted in which the full-scale range of fine ADC is consistent with the equivalent voltage to 1.5 LSB for coarse ADC. With this architecture, 10b resolution is not required for coarse ADC, and total resolution is decided by fine ADC.

原文English
頁面48-51
頁數4
DOIs
出版狀態Published - 1989
事件Proceedings of the 1989 Bipolar Circuits and Technology Meeting - Minneapolis, MN, USA
持續時間: 18 9月 198919 9月 1989

Conference

ConferenceProceedings of the 1989 Bipolar Circuits and Technology Meeting
城市Minneapolis, MN, USA
期間18/09/8919/09/89

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