0.5 V DD digitally controlled oscillators design with compensation techniques for PVT variations

Chia Wen Chang*, Shyh-Jye Jou, Yuan Hua Chu

*此作品的通信作者

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a low voltage and low power digitally controlled oscillator (DCO) with not only wide frequency range and high frequency resolution but also compensation techniques against PVT variations. The frequency range of the 0.5 V DD DCO, implemented in GP-65 nm LVT CMOS process, is from 278 MHz to 25 MHz for portable applications and consumes only 148 μW at 278 MHz and 28.5 μW at 25 MHz. Even in a dirty V DD /GND condition, the peak-to-peak and RMS period jitter are 98.7 and 12.7 ps, respectively. In addition, with compensation techniques used in this work, the effective frequency range is increased by 1.786 times. As a result, compensation techniques in this work are very suitable for the demand of robust design, especially in low-voltage systems or wide PVT environments.

原文English
主出版物標題Proceedings - 2011 IEEE 9th International Conference on ASIC, ASICON 2011
頁面606-609
頁數4
DOIs
出版狀態Published - 1 十二月 2011
事件2011 IEEE 9th International Conference on ASIC, ASICON 2011 - Xiamen, China
持續時間: 25 十月 201128 十月 2011

出版系列

名字Proceedings of International Conference on ASIC
ISSN(列印)2162-7541
ISSN(電子)2162-755X

Conference

Conference2011 IEEE 9th International Conference on ASIC, ASICON 2011
國家/地區China
城市Xiamen
期間25/10/1128/10/11

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