0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS

Yasuyuki Okuma*, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai

*此作品的通信作者

研究成果: Conference contribution同行評審

218 引文 斯高帕斯(Scopus)

摘要

Digital LDO is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

原文English
主出版物標題IEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
出版狀態Published - 13 12月 2010
事件32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
持續時間: 19 9月 201022 9月 2010

出版系列

名字Proceedings of the Custom Integrated Circuits Conference
ISSN(列印)0886-5930

Conference

Conference32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
國家/地區United States
城市San Jose, CA
期間19/09/1022/09/10

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