0.5 μm silicon bipolar transistor technology for analog applications

H. Nakajima*, N. Itoh, K. Inou, T. Iinuma, S. Matsuda, C. Yoshino, Y. Katsumata, H. Iwai

*此作品的通信作者

研究成果: Paper同行評審

2 引文 斯高帕斯(Scopus)

摘要

A silicon bipolar technology for low power analog applications with a 0.5 μm design rule has been developed. A maximum fT value of 24 GHz ( VCE = 2V, IC = 260 μA) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz ( VCC = 5V, IC = 600 μA).

原文English
頁面213-216
頁數4
DOIs
出版狀態Published - 1994
事件Proceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
持續時間: 10 10月 199411 10月 1994

Conference

ConferenceProceedings of the 1994 Bipolar/BiCMOS Circuits and Technology Meeting
城市Minneapolis, MN, USA
期間10/10/9411/10/94

指紋

深入研究「0.5 μm silicon bipolar transistor technology for analog applications」主題。共同形成了獨特的指紋。

引用此