0.3 μm BiCMOS technology for mixed analog/digital application systems

H. Nii*, T. Yoshino, K. Inoh, N. Itoh, H. Nakajima, H. Sugaya, H. Naruse, Y. Katsumata, H. Iwai

*此作品的通信作者

研究成果: Paper同行評審

3 引文 斯高帕斯(Scopus)

摘要

In this paper, 0.3 μm BiCMOS technology for mixed analog/digital application is presented. This technology includes high fmax and high BVceo NPN transistor, 0.3 μm CMOS, and passive elements. These elements are successfully implemented.

原文English
頁面68-71
頁數4
出版狀態Published - 1997
事件Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting - Minneapolis, MN, USA
持續時間: 28 9月 199730 9月 1997

Conference

ConferenceProceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting
城市Minneapolis, MN, USA
期間28/09/9730/09/97

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