摘要
This paper describes a leading-edge 0.15 μm CMOS logic foundry technology family. Advanced core devices using 20 angstroms oxides for 1.2-1.5 V operation (L G_min = 0.1 μm) support high-performance CPU and graphics applications. The technology supports also low-standby power applications with 26 angstroms oxide for 1.5 V operation. Periphery circuitry for 2.5 or 3.3 V compatibility use dual 50 or 65 angstroms gate oxides respectively. AlCu with low-k (FSG) is used for the seven-level metal interconnect system with extremely tight pitch (0.39 μm for M1 and 0.48 μm for intermediate levels). The aggressive design rules and border-less contacts/vias render an embedded (synchronous cache) 6T SRAM cell of 3.42 μm 2 demonstrated in a 2 Mb vehicle with very high yield. The overall process reliability is also shown to meet standard industry requirements.
原文 | English |
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頁(從 - 到) | 146-147 |
頁數 | 2 |
期刊 | Digest of Technical Papers - Symposium on VLSI Technology |
DOIs | |
出版狀態 | Published - 1 1月 2000 |
事件 | 2000 Symposium on VLSI Technology - Honolulu, HI, USA 持續時間: 13 6月 2000 → 15 6月 2000 |