TY - JOUR

T1 - 0.13-μm RF CMOS and varactors performance optimization by multiple gate layouts

AU - Ho, Chien Chih

AU - Kuo, Chin Wei

AU - Chan, Yi Jen

AU - Lien, Wan Yih

AU - Guo, Jyh-Chyurn

PY - 2004/12/1

Y1 - 2004/12/1

N2 - 0.13-μm radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (fT), associated power gain cutoff frequency (fmax), minimum noise figure (N Fmin), output power (Pout), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (WF) exists by trade-off among fT, f max, N Fmin, Pout, and PAE. Under fixed total width to achieve the same current drivability (I ds), the smaller WF and the larger finger number (NF) leads to higher fmax but lower f T due to trade-off between gate resistance (R g) and parasitic gate capacitance. As for N F min complicated by fT and Rg, counter-balance between parasitic gate capacitance and Rg leads to nearly constant N Fmin w.r.t, various splits of (W F, NF). Regarding Pout and PAE, WF of 4 μm and NF of 18 is the optimized layout parameter, which offers the maximum Pout of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 μm2 gate area varactor, and its tuning range is from 210 fF to 1.64 pF, where the maximum Cmax/Cmin, ratio is about 7.8.

AB - 0.13-μm radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (fT), associated power gain cutoff frequency (fmax), minimum noise figure (N Fmin), output power (Pout), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (WF) exists by trade-off among fT, f max, N Fmin, Pout, and PAE. Under fixed total width to achieve the same current drivability (I ds), the smaller WF and the larger finger number (NF) leads to higher fmax but lower f T due to trade-off between gate resistance (R g) and parasitic gate capacitance. As for N F min complicated by fT and Rg, counter-balance between parasitic gate capacitance and Rg leads to nearly constant N Fmin w.r.t, various splits of (W F, NF). Regarding Pout and PAE, WF of 4 μm and NF of 18 is the optimized layout parameter, which offers the maximum Pout of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 μm2 gate area varactor, and its tuning range is from 210 fF to 1.64 pF, where the maximum Cmax/Cmin, ratio is about 7.8.

KW - 0.13.μm CMOS

KW - N F

KW - RF power

KW - Varactor

UR - http://www.scopus.com/inward/record.url?scp=10644227835&partnerID=8YFLogxK

U2 - 10.1109/TED.2004.839868

DO - 10.1109/TED.2004.839868

M3 - Article

AN - SCOPUS:10644227835

VL - 51

SP - 2181

EP - 2185

JO - Ieee Transactions On Electron Devices

JF - Ieee Transactions On Electron Devices

SN - 0018-9383

IS - 12

ER -