0.12 μm raised gate/source/drain epitaxial channel NMOS technology

T. Ohguro*, H. Naruse, H. Sugaya, H. Kimijima, E. Morifuji, T. Yoshitomi, T. Morimoto, H. S. Momose, Y. Katsumata, H. Iwai

*此作品的通信作者

研究成果: Conference article同行評審

16 引文 斯高帕斯(Scopus)

摘要

We introduce a 0.12 μm nMOS technology with multi-Vth's for mixed high-speed digital and RF-analog applications. Though basically device parameter was determined by SIA roadmap, new structures such as undoped epitaxial channel and raised gate/source/drain were applied to a 0.12 μm nMOS. This device has high fT and low noise figure which are very important for RF analog circuit design. High Idrive/Ioff ratio for drain current was also realized.

原文English
頁(從 - 到)927-930
頁數4
期刊Technical Digest - International Electron Devices Meeting
DOIs
出版狀態Published - 1998
事件Proceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
持續時間: 6 12月 19989 12月 1998

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