0. 8 mu m Bi-CMOS TECHNOLOGY WITH HIGH F//T ION-IMPLANTED EMITTER BIPOLAR TRANSISTOR.

H. Iwai*, G. Sasaki, Y. Unno, Y. Niitsu, M. Norishima, Y. Sugimoto, K. Kanzaki

*此作品的通信作者

研究成果: Conference article同行評審

18 引文 斯高帕斯(Scopus)

摘要

A submicrometer Bi-CMOS (bipolar-CMOS) technology with a direct ion-implanted emitter bipolar transistor was developed using an 0. 8- mu m CMOS process. For the bipolar transistor, an ion-implanted emitter structure was chosen to minimize the production cost. By optimizing the bipolar transistor, a sufficiently high performance for Bi-CMOS gates was obtained. The fabrication-process sequences and resulting device characteristics are described.

原文English
頁(從 - 到)28-31
頁數4
期刊Technical Digest - International Electron Devices Meeting
DOIs
出版狀態Published - 1987

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