A submicrometer Bi-CMOS (bipolar-CMOS) technology with a direct ion-implanted emitter bipolar transistor was developed using an 0. 8- mu m CMOS process. For the bipolar transistor, an ion-implanted emitter structure was chosen to minimize the production cost. By optimizing the bipolar transistor, a sufficiently high performance for Bi-CMOS gates was obtained. The fabrication-process sequences and resulting device characteristics are described.
|頁（從 - 到）||28-31|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1987|