三維積體電路之堆疊誤差電性量測設計

@misc{ae6e70b7723949c9bdc35491cffc1d81,

title = "三維積體電路之堆疊誤差電性量測設計",

author = "Kuan-Neng Chen",

year = "2014",

month = mar,

day = "5",

language = "???core.languages.zh_TW???",

type = "Patent",

note = "10-1373267",

}

三維積體電路之堆疊誤差電性量測設計. / Chen, Kuan-Neng (Inventor).
專利號: 10-1373267. 3月 05, 2014.

研究成果: Patent

TY - PAT

T1 - 三維積體電路之堆疊誤差電性量測設計

AU - Chen, Kuan-Neng

PY - 2014/3/5

Y1 - 2014/3/5

M3 - Patent

M1 - 10-1373267

ER -

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