Yueh-Chin Lin

2022

Investigation of p-GaN Gate HEMT using Removal Si Substrate and part of Buffer Layer

Lin, Y., Chiu, Y. S. & Chang, E. Y., 2022, Proceedings - 2022 IET International Conference on Engineering Technologies and Applications, IET-ICETA 2022. Institute of Electrical and Electronics Engineers Inc., (Proceedings - 2022 IET International Conference on Engineering Technologies and Applications, IET-ICETA 2022).

研究成果: Conference contribution › 同行評審

2013

An integrated air gap structure to achieve high-performance TSV interconnects for 28nm 3D-IC integration

Liao, E. B., Cheng, K. W., Chen, Y. H., Teng, H. A., Chen, Y. H., Tseng, Y. C., Tsai, W. C., Chen, J. H., Lin, T. C., Yang, K. F., Lin, Y. C., Chang, H. B., Wei, T. S., Chen, H. Y., Chen, M. F., Hsieh, C. C., Wu, T. J., Wu, C. H., Shih, D. Y. & Chiou, W. C. 及其他2, Jeng, S. P. & Yu, C. H., 6月 2013, 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. p. T42-T43 6576678. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution › 同行評審

5 引文斯高帕斯（Scopus）

2012

An ultra-thin interposer utilizing 3D TSV technology

Chiou, W. C., Yang, K. F., Yeh, J. L., Wang, S. H., Liou, Y. H., Wu, T. J., Lin, J. C., Huang, C. L., Lu, S. W., Hsieh, C. C., Teng, H. A., Chiu, C. C., Chang, H. B., Wei, T. S., Lin, Y. C., Chen, Y. H., Tu, H. J., Ko, H. D., Yu, T. H. & Hung, J. P. 及其他10, Tsai, P. H., Yeh, D. C., Wu, W. C., Su, A. J., Chiu, S. L., Hou, S. Y., Shih, D. Y., Chen, K. H., Jeng, S. P. & Yu, C. H., 2012, 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. p. 107-108 2 p. 6242484. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution › 同行評審

12 引文斯高帕斯（Scopus）

High-aspect ratio through silicon via (TSV) technology

Chang, H. B., Chen, H. Y., Kuo, P. C., Chien, C. H., Liao, E. B., Lin, T. C., Wei, T. S., Lin, Y. C., Chen, Y. H., Yang, K. F., Teng, H. A., Tsai, W. C., Tseng, Y. C., Chen, S. Y., Hsieh, C. C., Chen, M. F., Liu, Y. H., Wu, T. J., Hou, S. Y. & Chiou, W. C. 及其他2, Jeng, S. P. & Yu, C. H., 2012, 2012 Symposium on VLSI Technology, VLSIT 2012 - Digest of Technical Papers. p. 173-174 2 p. 6242517. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution › 同行評審

20 引文斯高帕斯（Scopus）

2011

Orthotropic stress field induced by TSV and its impact on device performance

Hsieh, C. C., Teng, H. A., Jeng, S. P., Jan, S. B., Chen, M. F., Chang, J. H., Chang, C. H., Yang, K. F., Lin, Y. C., Wu, T. J., Chiou, W. C., Hou, S. Y. & Yu, D. C. H., 2011, 2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011. 5940276. (2011 IEEE International Interconnect Technology Conference and 2011 Materials for Advanced Metallization, IITC/MAM 2011).

研究成果: Conference contribution › 同行評審

11 引文斯高帕斯（Scopus）

Yield and reliability of 3DIC technology for advanced 28nm node and beyond

Yang, K. F., Wu, T. J., Chiou, W. C., Chen, M. F., Lin, Y.-C., Tsai, F. W., Hsieh, C. C., Chang, C. H., Wu, W. J., Chen, Y. H., Chen, T. Y., Wang, H. R., Lin, I. C., Jan, S. B., Wang, R. D., Lu, Y. J., Shih, Y. C., Teng, H. A., Tsai, C. S. & Chang, M. N. 及其他4, Chen, K., Hou, S. Y., Jeng, S. P. & Yu, C. H., 14 6月 2011, 2011 Symposium on VLSI Technology, VLSIT 2011 - Digest of Technical Papers. p. 140-141 2 p. 5984674. (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution › 同行評審

10 引文斯高帕斯（Scopus）

2010

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Lin, J. C., Chiou, W. C., Yang, K. F., Chang, H. B., Lin, Y. C., Liao, E. B., Hung, J. P., Lin, Y. L., Tsai, P. H., Shih, Y. C., Wu, T. J., Wu, W. J., Tsai, F. W., Huang, Y. H., Wang, T. Y., Yu, C. L., Chang, C. H., Chen, M. F., Hou, S. Y. & Tung, C. H. 及其他2, Jeng, S. P. & Yu, D. C. H., 2010, 2010 IEEE International Electron Devices Meeting, IEDM 2010. p. 2.1.1-2.1.4 5703277. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution › 同行評審

52 引文斯高帕斯（Scopus）

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Wu, C. C., Lin, D. W., Keshavarzi, A., Huang, C. H., Chan, C. T., Tseng, C. H., Chen, C. L., Hsieh, C. Y., Wong, K. Y., Cheng, M. L., Li, T. H., Lin, Y. C., Yang, L. Y., Lin, C. P., Hou, C. S., Lin, H. C., Yang, J. L., Yu, K. F., Chen, M. J. & Hsieh, T. H. 及其他43, Peng, Y. C., Chou, C. H., Lee, C. J., Huang, C. W., Lu, C. Y., Yang, F. K., Chen, H. K., Weng, L. W., Yen, P. C., Wang, S. H., Chang, S. W., Chuang, S. W., Gan, T. C., Wu, T. L., Lee, T. Y., Huang, W. S., Huang, Y. J., Tseng, Y. W., Wu, C. M., Ou-Yang, E., Hsu, K. Y., Lin, L. T., Wang, S. B., Kwok, T. M., Su, C. C., Tsai, C. H., Huang, M. J., Lin, H. M., Chang, A. S., Liao, S. H., Chen, L. S., Chen, J. H., Lim, P. S., Yu, X. F., Ku, S. Y., Lee, Y. B., Hsieh, P. C., Wang, P. W., Chiu, Y. H., Lin, S. S., Tao, H. J., Cao, M. & Mii, Y. J., 2010, 2010 IEEE International Electron Devices Meeting, IEDM 2010. p. 27.1.1-27.1.4 5703430. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution › 同行評審

64 引文斯高帕斯（Scopus）

2009

Enabling 3D-IC foundry technologies for 28 nm node and beyond: Through-silicon-via integration with high throughput die-to-wafer stacking

Chen, D. Y., Chiou, W. C., Chen, M. F., Wang, T. D., Ching, K. M., Tu, H. J., Wu, W. J., Yu, C. L., Yang, K. F., Chang, H. B., Tseng, M. H., Hsiao, C. W., Lu, Y. J., Hu, H. P., Lin, Y. C., Hsu, C. S., Shue, W. S. & Yu, C. H., 2009, 2009 International Electron Devices Meeting, IEDM 2009 - Technical Digest. p. 14.3.1-14.3.4 5424350. (Technical Digest - International Electron Devices Meeting, IEDM).

研究成果: Conference contribution › 同行評審

28 引文斯高帕斯（Scopus）

林 岳欽

研究成果

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林岳欽