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查看斯高帕斯 (Scopus) 概要
林 岳欽
約聘研究員
電子與資訊研究中心
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242
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8
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45
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4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
43
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4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2009
2024
每年研究成果
概覽
指紋
網路
研究成果
(25)
類似的個人檔案
(5)
指紋
查看啟用 Yueh-Chin Lin 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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重量
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Keyphrases
GaN HEMT
100%
Ka-band
84%
AlGaN-GaN
70%
Band Application
53%
High Electron Mobility Transistor
43%
Through Silicon via
35%
3D IC
29%
Device Performance
28%
Foundry Technology
23%
OIP3
21%
Gate Structure
20%
CMOS Devices
19%
NFmin
18%
Millimeter Wave
17%
Aluminum Oxide
17%
Aluminum Gallium Nitride (AlGaN)
17%
P-GaN
17%
Si Substrate
17%
Low Noise
17%
High Performance
17%
High Linearity
17%
Gate Length
16%
Power Added Efficiency
15%
Third-order Intercept Point
14%
Minimum Noise Figure
12%
Fmax
12%
Electrical Characteristics
11%
Threshold Voltage
11%
Source Resistance
11%
Gate Width
11%
Power Performance
11%
Noise Performance
10%
Millimeter-wave Applications
10%
Integrated Circuits
10%
High Density
10%
Noise Figure
10%
Radio Frequency Performance
10%
Device Linearity
10%
Parasitic Capacitance
10%
Metallized
10%
Enhancement-mode (E-mode)
10%
Barrier Layer
9%
InGaAs Channel
8%
28nm Node
8%
InAlAs
8%
FinFET CMOS
8%
Surface Treatment
8%
Insulator
8%
Al2O3 Gate Dielectric
8%
Backside via
8%
Engineering
Ka-Band
75%
Power Density
29%
Device Performance
27%
Nodes
26%
Three Dimensional Integrated Circuits
26%
Millimeter Wave
26%
Noise Figure
24%
Order Intercept Point
19%
Interconnects
18%
Power Added Efficiency
17%
Output Power
17%
Gate Length
16%
Cutoff Frequency
13%
Metallizations
13%
Gate Dielectric
13%
Integrated Circuit
13%
Gate Width
12%
Lithography
11%
Buffer Layer
11%
Noise Performance
11%
Barrier Layer
11%
Radio Frequency
10%
Parasitic Capacitance
10%
Stress Field
8%
Current Drain
8%
Indium Gallium Arsenide
8%
Surface Treatment Technique
8%
Metal Gate
8%
Interposer
8%
Induced Stress
8%
Si Substrate
8%
Source Resistance
8%
High Aspect Ratio
8%
Ohmic Contacts
8%
Phase Composition
8%
Electrical Performance
8%
Scattering Parameters
7%
Current Ratio
7%
Intermodulation
7%
Enabling Technology
7%
Current Source
6%
Max
6%
Back Side
5%
Thinning Process
5%
Gate Stack
5%
Manufacturability
5%
