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查看斯高帕斯 (Scopus) 概要
游 逸平
副教授
資訊學院碩士在職專班
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227
引文
8
h-指數
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29
引文
4
h-指數
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15
引文
2
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2005
2025
每年研究成果
概覽
指紋
網路
計畫
(19)
研究成果
(41)
獎項
(8)
類似的個人檔案
(1)
指紋
查看啟用 Yi-Ping You 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Computer Science
Analytical Model
7%
Binary Translator
9%
Branch Instruction
7%
Case Study
7%
Checkpointing
8%
Code Generation
7%
Compilation
24%
Compiler
100%
Compiler Optimization
26%
Component Analysis
7%
Compressed Instruction
7%
Computer Architecture
7%
Concurrency
9%
Cyber Physical Systems
7%
Data Mapping
7%
Deep Learning Method
10%
Deep Learning Model
7%
Dynamic Voltage Scaling
15%
Embedded System
21%
Energy Consumption
12%
Energy Dissipation
8%
Experimental Result
19%
File Structure
9%
Floating Point
7%
Function Inlining
7%
Graphics Processing Unit
40%
Guided Optimization
7%
Inlining
15%
Mobile Device
6%
Multimedia Application
6%
Multitasking
15%
Multithreading
7%
Network Security
7%
Open Research
7%
OpenCL
23%
Optimization Sequence
7%
Parallel Program
7%
Performance Improvement
7%
Point Instruction
7%
Power Consumption
10%
Power Optimization
10%
Programming Model
6%
Reduced Instruction Set Computer
7%
Register Allocation
32%
Register Allocator
7%
Stepping Stone
7%
Total Energy Consumption
7%
Tuning Phase
7%
Virtual Machine
16%
Web Application
7%
Keyphrases
AArch64
7%
Allocator
7%
Autotuners
15%
Code Generation
7%
Code Motion
7%
Code Size Reduction
7%
Compiler
41%
Compiler Analysis
12%
Compiler Optimization
11%
Compiler Support
17%
Compiler Tools
6%
Deep Learning Operators
7%
Distributed Register
11%
DSP Core
8%
DSP Processor
22%
Energy Consumption
9%
Energy-aware
7%
Floating-point
7%
Function Inlining
7%
Gate Control
8%
Graphics Processing Unit
15%
High Performance
6%
Input Buffer
7%
Instruction Set
11%
Interference-aware
7%
Leakage Power
12%
Leakage Power Reduction
15%
Low Power Techniques
7%
Microprocessor
7%
Multitasking Framework
7%
Network Security Processor
7%
Neural Operator
7%
Non-local Consciousness
7%
Open Computing Language
7%
Open Research
6%
Optimization Sequence
7%
Output Buffer
7%
Ping-pong
8%
Power Gating
20%
Register Allocation
6%
Register File
21%
Scheduling Methodology
7%
Scheduling Policy
6%
Sequence Prediction
7%
Shader Processors
15%
Static Region
7%
Structured Concurrency
7%
Subsequence
7%
VLIW DSP
30%
X86-64
7%
