Wei-Zen Chen

查看斯高帕斯 (Scopus) 概要

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電子郵件wzchenmail.nctu.edutw
網站http://www.alab.ee.nctu.edu.tw/wpmu/ed307/faculty/%E9%99%B3%E5%B7%8D%E4%BB%81/

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每年研究成果

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50 Conference contribution
30 Article
20 Patent
6 Paper
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30結果

篩選

2022
A 1.68-23.2-Gb/s Reference-Less Half-Rate Receiver With an ISI-Tolerant Unlimited Range Frequency Detector
Huang, Y. P., Chang, Y. W. & Chen, W. Z., 2022, 於: IEEE Solid-State Circuits Letters. 5, p. 186-189 4 p.
研究成果: Article › 同行評審
A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fs<inline-formula> <tex-math notation="LaTeX">$_{\mathrm{rms}}$</tex-math> </inline-formula> Resolution With Background Self-Calibration
Jian, W. J. & Chen, W. Z., 2022, (Accepted/In press) 於: IEEE Journal of Solid-State Circuits. p. 1-9 9 p.
研究成果: Article › 同行評審
2021
A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration
Lin, Y. T., Xu, T. W. & Chen, W. Z., 8月 2021, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 68, 8, p. 2820 - 2824 5 p.
研究成果: Article › 同行評審
2 引文斯高帕斯（Scopus）
2020
Exploring Multiple Analog Placements with Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP
Patyal, A., Pan, P. C., K. A., A., Chen, H. M. & Chen, W. Z., 12月 2020, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39, 12, p. 5056-5068 13 p., 9005191.
研究成果: Article › 同行評審
3 引文斯高帕斯（Scopus）
2019
A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery
Lee, Y. S., Ho, W. H. & Chen, W-Z., 1 8月 2019, 於: IEEE Journal of Solid-State Circuits. 54, 8, p. 2243-2254 12 p., 8698805.
研究成果: Article › 同行評審
11 引文斯高帕斯（Scopus）
2017
A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS
Huang, S. H. & Chen, W-Z., 1 3月 2017, 於: IEEE Journal of Solid-State Circuits. 52, 3, p. 747-756 10 p., 7858746.
研究成果: Article › 同行評審
31 引文斯高帕斯（Scopus）
2016
Distortion-characteristic estimation predistorter for high efficiency power amplifiers
Ren, Z., Chen, H. H. & Chen, W-Z., 1 12月 2016, 於: IET Signal Processing. 10, 9, p. 1024-1030 7 p.
研究成果: Article › 同行評審
1 引文斯高帕斯（Scopus）
2015
A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression
Su, M. C., Chen, W-Z., Wu, P. S., Chen, Y. H., Lee, C. C. & Jou, S-J., 1 3月 2015, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 62, 3, p. 743-751 9 p., 06977996.
研究成果: Article › 同行評審
8 引文斯高帕斯（Scopus）
A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery
Hong, Z. H., Liu, Y. C. & Chen, W-Z., 1 11月 2015, 於: IEEE Journal of Solid-State Circuits. 50, 11, p. 2625-2634 10 p., 7275066.
研究成果: Article › 同行評審
16 引文斯高帕斯（Scopus）
A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs
Su, M. C., Jou, S-J. & Chen, W-Z., 1 4月 2015, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 4, p. 766-770 5 p., 6798731.
研究成果: Article › 同行評審
15 引文斯高帕斯（Scopus）
2014
A 160-GHz frequency-translation phase-locked loop with RSSI assisted frequency acquisition
Chen, W-Z., Lu, T. Y., Wang, Y. T., Jian, J. T., Yang, Y. H. & Chang, K. T., 1 1月 2014, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 6, p. 1648-1655 8 p., 6728756.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
2013
The development of a non-surgical direct drive hearing device with a wireless actuator coupled to the tympanic membrane
Song, Y. L., Jian, J. T., Chen, W-Z., Shih, C. H., Chou, Y. F., Liu, T. C. & Lee, C. F., 29 7月 2013, 於: Applied Acoustics. 74, 12, p. 1511-1518 8 p.
研究成果: Article › 同行評審
10 引文斯高帕斯（Scopus）
Wide tunning range 60 GHz VCO and 40 GHz DCO using single variable inductor
Lu, T. Y., Yu, C. Y., Chen, W-Z. & Wu, C-Y., 1 1月 2013, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 60, 2, p. 257-267 11 p., 6336804.
研究成果: Article › 同行評審
48 引文斯高帕斯（Scopus）
2012
A 2.4 GHz reference-less receiver for 1 Mbps QPSK demodulation
Chen, W-Z., Lu, T. Y., Ou, W. W., Chou, S. T. & Yang, S. Y., 1 1月 2012, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 59, 3, p. 505-514 10 p., 2165417.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
A 3-10 GHz, 14 bands CMOS frequency synthesizer with spurs reduction for MB-OFDM UWB system
Lu, T. Y. & Chen, W-Z., 1 5月 2012, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 5, p. 948-958 11 p., 5756216.
研究成果: Article › 同行評審
13 引文斯高帕斯（Scopus）
2011
A 10-Gb/s OEIC with meshed spatially-modulated photo detector in 0.18-μm CMOS technology
Huang, S. H., Chen, W-Z., Chang, Y. W. & Huang, Y. T., 1 5月 2011, 於: IEEE Journal of Solid-State Circuits. 46, 5, p. 1158-1169 12 p., 5733374.
研究成果: Article › 同行評審
80 引文斯高帕斯（Scopus）
A 38/114 GHz switched-mode and synchronous lock standing wave oscillator
Lu, T. Y. & Chen, W-Z., 1 1月 2011, 於: IEEE Microwave and Wireless Components Letters. 21, 1, p. 40-42 3 p., 5659874.
研究成果: Article › 同行評審
6 引文斯高帕斯（Scopus）
2010
A 7.1 mW, 10 GHz all digital frequency synthesizer with dynamically reconfigured digital loop filter in 90 nm CMOS technology
Yang, S. Y., Chen, W-Z. & Lu, T. Y., 1 3月 2010, 於: IEEE Journal of Solid-State Circuits. 45, 3, p. 578-586 9 p., 5419178.
研究成果: Article › 同行評審
46 引文斯高帕斯（Scopus）
2009
A single-chip 2.5-Gb/s CMOS burst-mode optical receiver
Chen, W-Z., Gan, R. M. & Huang, S. H., 1 12月 2009, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 56, 10, p. 2325-2331 7 p., 4738421.
研究成果: Article › 同行評審
3 引文斯高帕斯（Scopus）
2008
Low-power programmable pseudorandom word generator and clock multiplier unit for high-speed SerDes applications
Chen, W-Z. & Huang, G. S., 1 7月 2008, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 55, 6, p. 1495-1501 7 p.
研究成果: Article › 同行評審
4 引文斯高帕斯（Scopus）
2007
A 90-dBΩ 10-Gb/s optical receiver analog front-end in a 0.18-μm CMOS technology
Chen, W-Z. & Lin, D. S., 1 3月 2007, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15, 3, p. 358-365 8 p.
研究成果: Article › 同行評審
7 引文斯高帕斯（Scopus）
A monolithic current-mode buck converter with advanced control and protection circuits
Ma, F. F., Chen, W-Z. & Wu, J. C., 1 9月 2007, 於: IEEE Transactions on Power Electronics. 22, 5, p. 1836-1846 11 p.
研究成果: Article › 同行評審
143 引文斯高帕斯（Scopus）
Three-dimensional fully symmetric inductors, transformer, and balun in CMOS technology
Chen, W-Z., Chen, W. H. & Hsu, K. C., 1 7月 2007, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 54, 7, p. 1413-1423 11 p.
研究成果: Article › 同行評審
35 引文斯高帕斯（Scopus）
2006
Design and anaylsis of A 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology
Chen, W-Z. & Lu, C. H., 1 5月 2006, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 53, 5, p. 977-983 7 p.
研究成果: Article › 同行評審

開啟存取
10 引文斯高帕斯（Scopus）
2005
A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end
Chen, W-Z., Cheng, Y. L. & Lin, D. S., 1 6月 2005, 於: IEEE Journal of Solid-State Circuits. 40, 6, p. 1388-1396 9 p.
研究成果: Article › 同行評審
110 引文斯高帕斯（Scopus）
2004
A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process
Chen, W-Z., Chang, J. X., Hong, Y. J., Wong, M. T. & Kuo, C. L., 1 1月 2004, 於: IEEE Journal of Solid-State Circuits. 39, 1, p. 234-237 4 p.
研究成果: Article › 同行評審
4 引文斯高帕斯（Scopus）
2002
A 2.5 Gbps CMOS optical receiver analog front-end
Chen, W-Z. & Lu, C. H., 1 1月 2002, 於: Proceedings of the Custom Integrated Circuits Conference. p. 359-362 4 p.
研究成果: Article › 同行評審
38 引文斯高帕斯（Scopus）
2001
Bandwidth enhancement techniques for transimpedance amplifier in cmos technologies
Lu, C. H. & Chen, W-Z., 1 1月 2001, 於: European Solid-State Circuits Conference. p. 174-177 4 p., 1471361.
研究成果: Article › 同行評審
3 引文斯高帕斯（Scopus）
1999
2-V, 1.8-GHz BJT phase-locked loop
Chen, W-Z. & Wu, J-T., 6月 1999, 於: IEEE Journal of Solid-State Circuits. 34, 6, p. 784-789 6 p.
研究成果: Article › 同行評審
1998
A 2-V 2-GHz BJT variable frequency oscillator
Chen, W-Z. & Wu, J-T., 1 9月 1998, 於: IEEE Journal of Solid-State Circuits. 33, 9, p. 1406-1410 5 p., 711339.
研究成果: Article › 同行評審

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