每年專案
個人檔案
研究專長
混合信號積體電路設計、高頻電路設計、通訊系統
經歷
1999/04~1999/07 工業技術研究院約聘人員
1999/08~2002/07 國立中央大學電機工程學系助理教授
2002/08~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, National Chiao Tung University
外部位置
指紋
查看啟用 Wei-Zen Chen 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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網路
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料,或
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A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector
Huang, Y. P., Chang, Y. W. & Chen, W. Z., 2021, Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference).研究成果: Conference contribution › 同行評審
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A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction
Lu, Y. S., Lee, C. L. & Chen, W. Z., 2021, Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference).研究成果: Conference contribution › 同行評審
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A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration
Lin, Y. T., Xu, T. W. & Chen, W. Z., 8月 2021, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 68, 8, p. 2820 - 2824 5 p.研究成果: Article › 同行評審
1 引文 斯高帕斯(Scopus) -
A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration
Liao, Y. S. & Chen, W. Z., 2021, Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference. Institute of Electrical and Electronics Engineers Inc., (Proceedings - A-SSCC 2021: IEEE Asian Solid-State Circuits Conference).研究成果: Conference contribution › 同行評審
1 引文 斯高帕斯(Scopus) -
F6: Optical and Electrical Transceivers for 400GbE and beyond
Carusone, T. C., Shekhar, S., Frans, Y., Chen, W. Z., Toifl, T., Nagatani, M., Dielacher, F. & Redman-White, W., 13 2月 2021, 於: Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 64, p. 533-536 4 p., 9365982.研究成果: Editorial