每年專案
個人檔案
研究專長
奈米記憶體元件、分子電子元件、奈米製程技術、半導體物理
經歷
2000~2004 台積電先進模組技術處資深工程師
2008~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, 電機工程, Cornell University
外部位置
指紋
查看啟用 Tuo-Hung Hou 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 1 類似的個人檔案
過去五年中的合作和熱門研究領域
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
專案
- 33 已完成
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探索摩爾定律的第三維度:高成本效益之多層堆疊式二維奈米片電晶體
Hou, T.-H. (PI)
1/08/23 → 31/07/24
研究計畫: Other Government Ministry Institute
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超低能耗記憶體內運算技術–從關鍵元件開發到仿生晶片設計之跨層級優化
Hou, T.-H. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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探索摩爾定律的第三維度:高成本效益之多層堆疊式二維奈米片電晶體
Hou, T.-H. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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超低能耗記憶體內運算技術–從關鍵元件開發到仿生晶片設計之跨層級優化
Hou, T.-H. (PI)
1/08/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application
Lin, K. C., Zuo, H., Wang, H. Y., Huang, Y. P., Wu, C. H., Guo, Y. C., Jou, S. J., Hou, T. H. & Chang, T. S., 2024, 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (Proceedings -Design, Automation and Test in Europe, DATE).研究成果: Conference contribution › 同行評審
1 引文 斯高帕斯（Scopus） -
An RRAM-Based 40.6 TOPS/W Energy-Efficient AI Inference Accelerator with Quad Neuromorphic-Processor-Unit for Highly Contrast Recognition
Lin, Y. L., Liu, Y. R., Kao, T. C., Lee, M. Y., Guo, J. C., Hou, T. H. & Chung, S. S., 2024, 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings).研究成果: Conference contribution › 同行評審
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CMOS-RRAM based In-Memory Hamming Distance Calculation Technique
Kumar, M., Wu, M. H., Hou, T. H. & Suri, M., 2024, IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024. Institute of Electrical and Electronics Engineers Inc., (IEEE Electron Devices Technology and Manufacturing Conference: Strengthening the Globalization in Semiconductors, EDTM 2024).研究成果: Conference contribution › 同行評審
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CMOS-RRAM Based Non-Volatile Ternary Content Addressable Memory (nvTCAM)
Kumar, M., Wu, M. H., Hou, T. H. & Suri, M., 2024, 於: IEEE Transactions on Nanotechnology. 23, p. 203-207 5 p.研究成果: Article › 同行評審
4 引文 斯高帕斯（Scopus） -
Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security
Lin, C. S., Chiou, B. C., Yang, Y. J., Su, J. W., Tseng, K. H., Ho, Y. T., Lai, C. M., Li, S. H., Chang, T. S., Chang, S. M., Sheu, S. S., Lo, W. C., Chang, S. C. & Hou, T. H., 2024, 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).研究成果: Conference contribution › 同行評審
獎項
活動
- 1 Editorial work
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Scientific Reports (事件)
Hou, T.-H. (Member of editorial board)
1 1月 2018 → 31 12月 2018活動: Editorial work