Tien-Sheng Chao

Article

Plasma-process-induced damage in sputtered TiN metal-gate capacitors with ultrathin nitrided oxides

Chen, C. C., Lin, H-C., Chang, C. Y., Chao, T-S., Huang, T. Y. & Liang, M. S., 8月 2000, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 39, 8, p. 4733-4737 5 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Polycrystalline silicon thin-film transistor with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation

Wu, S. C., Hou, T-H., Chuang, S. H., Chou, H. C., Chao, T-S. & Lei, T. F., 1 12月 2012, 於: Solid-State Electronics. 78, p. 11-16 6 p.

研究成果: Article › 同行評審

Poly-oxide/poly-Si/SiO₂/Si structure for ellipsometry measurement

Chao, T-S., Lee, C. L., Lei, T. F. & Yen, Y. T., 4 6月 1992, 於: Electronics Letters. 28, 12, p. 1144-1145 2 p.

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2 引文斯高帕斯（Scopus）

Poly-Si thin-film transistor nonvolatile memory using Ge nanocrystals as a charge trapping layer deposited by the low-pressure chemical vapor deposition

Kuo, P. Y., Chao, T-S., Huang, J. S. & Lei, T. F., 12 2月 2009, 於: IEEE Electron Device Letters. 30, 3, p. 234-236 3 p.

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6 引文斯高帕斯（Scopus）

Positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer-induced local-tensile-strained HfO₂ nMOSFET

Wu, W. C., Chao, T-S., Chiu, T. H., Wang, J. C., Lai, C. S., Ma, M. W. & Lo, W. C., 8 12月 2008, 於: IEEE Electron Device Letters. 29, 12, p. 1340-1343 4 p.

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15 引文斯高帕斯（Scopus）

Post-Polysilicon Gate-Process-Induced Degradation on Thin Gate Oxide

Lai, C. S., Lei, T. F., Lee, C. L. & Chao, T-S., 1 1月 1995, 於: IEEE Electron Device Letters. 16, 11, p. 470-472 3 p.

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3 引文斯高帕斯（Scopus）

Prospect of cobalt-mix-tetraethoxysilane method on localized lateral growth of carbon nanotubes for both p- and n-type field effect transistors

Chen, B. H., Lin, H-C., Huang, T. Y., Wei, J. H., Hwang, C. L., Lo, P. Y., Tsai, M. J. & Chao, T-S., 9 10月 2006, 於: Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures. 24, 5, p. 2282-2290 9 p.

研究成果: Article › 同行評審

Reduced Reverse Narrow Channel Effect in Thin SOI nMOSFETs

Chang, C. Y., Chang, S. J., Chao, T-S., Wu, S. D. & Huang, T. Y., 1 9月 2000, 於: IEEE Electron Device Letters. 21, 9, p. 460-462 3 p.

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9 引文斯高帕斯（Scopus）

Reduction of donor-like interface traps of n-type metal-oxide-semiconductor field-effect-transistors using hydrogen-annealed wafer and in-situ HF-vapor treatment

Chao, T-S., Lin, Y. H. & Yang, W. L., 10 1月 2006, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 1 A, p. 61-63 3 p.

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Reduction of nickel-silicided junction leakage by nitrogen ion implantation

Chao, T-S. & Lee, L. Y., 1 2月 2002, 於: Japanese Journal of Applied Physics, Part 2: Letters. 41, 2 A

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9 引文斯高帕斯（Scopus）

Reliability analysis of symmetric vertical-channel nickel-salicided poly-Si thin-film transistors

Wu, Y. H., Lin, J. W., Lu, Y. H., Kuo, R. H., Yen, L. C., Chen, Y. H., Liao, C. C., Kuo, P. Y. & Chao, T-S., 19 6月 2012, 於: IEEE Transactions on Electron Devices. 59, 8, p. 2160-2166 7 p., 6215029.

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1 引文斯高帕斯（Scopus）

Reliability mechanisms of LTPS-TFT with HfO ₂ gate dielectric: PBTI, NBTI, and hot-carrier stress

Ma, M. W., Chen, C. Y., Wu, W. C., Su, C. J., Kao, K. H., Chao, T-S. & Lei, T. F., 1 5月 2008, 於: IEEE Transactions on Electron Devices. 55, 5, p. 1153-1160 8 p.

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42 引文斯高帕斯（Scopus）

Reliability of p-Type Pi-Gate Poly-Si Nanowire Channel Junctionless Accumulation-Mode FETs

Hsieh, D. R., Lin, K. C., Lee, C. C. & Chao, T. S., 6月 2021, 於: IEEE Transactions on Electron Devices. 68, 6, p. 2647-2652 6 p., 9429915.

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2 引文斯高帕斯（Scopus）

Robust data retention and superior endurance of silicon-oxide-nitride- oxide-silicon-type nonvolatile memory with NH ₃-plasma-treated and pd-nanocrystal-embedded charge storage layer

Liu, S. H., Yang, W. L., Hsiao, Y. P. & Chao, T-S., 1 4月 2012, 於: Japanese journal of applied physics. 51, 4 PART 2, 04DD05.

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8 引文斯高帕斯（Scopus）

Robust ultrathin oxynitride dielectrics by NH₃ nitridation and N₂O RTA treatment

Pan, T. M., Lei, T. F. & Chao, T-S., 1 8月 2000, 於: IEEE Electron Device Letters. 21, 8, p. 378-380 3 p.

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18 引文斯高帕斯（Scopus）

Role of Nitrogen in Ferroelectricity of HfₓZr₁₋ₓO₂-Based Capacitors With Metal-Ferroelectric-Insulator-Metal Structure

Hsieh, D. R., Lee, C. C. & Chao, T. S., 2022, (Accepted/In press) 於: IEEE Transactions on Electron Devices.

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1 引文斯高帕斯（Scopus）

Scanning probe lithography of self-assembled N-(2-Aminoethyl)-3- aminopropyltrimethoxysilane monolayers on SiO₂ surface

Wu, C. H., Sheu, J-T., Chen, C. H. & Chao, T-S., 20 9月 2007, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 46, 9 B, p. 6272-6276 5 p.

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3 引文斯高帕斯（Scopus）

Selective deposition of gold particles on dip-pen nanolithography patterns on silicon dioxide surfaces

Sheu, J-T., Wu, C. H. & Chao, T-S., 25 4月 2006, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 4 B, p. 3693-3697 5 p.

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8 引文斯高帕斯（Scopus）

Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors

Chung, C. C. C., Ko, C. M. & Chao, T. S., 2019, 於: IEEE Journal of the Electron Devices Society. 7, 1, p. 959-963 5 p., 8843925.

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1 引文斯高帕斯（Scopus）

Simultaneous activation and crystallization by low-temperature microwave annealing for improved quality of amorphous silicon thin-film transistors

Lu, Y. L., Lee, Y. J. & Chao, T-S., 1 12月 2012, 於: ECS Solid State Letters. 1, 1

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4 引文斯高帕斯（Scopus）

Simultaneous Quality Improvement of Tunneling- and Interpoly-Oxides of Nonvolatile Memory Devices by NH₃ and N₂O Nitridation

Chao, T-S. & Chang, T. H., 1 11月 2003, 於: IEEE Transactions on Electron Devices. 50, 11, p. 2300-2302 3 p.

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1 引文斯高帕斯（Scopus）

Si nanocrystal memory devices self-assembled by in situ rapid thermal annealing of ultrathin a -Si on SiO₂

Chen, J. H., Lei, T. F., Landheer, D., Wu, X., Liu, J. & Chao, T-S., 17 8月 2007, 於: Electrochemical and Solid-State Letters. 10, 10

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16 引文斯高帕斯（Scopus）

SONOS memories with embedded silicon nanocrystals in nitride

Liu, M-C., Chiang, T. Y., Kuo, P. Y., Chou, M. H., Wu, Y. H., You, H. C., Cheng, C. H., Liu, S. H., Yang, W. L., Lei, T. F. & Chao, T-S., 1 7月 2008, 於: Semiconductor Science and Technology. 23, 7, 075033.

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8 引文斯高帕斯（Scopus）

Spatially-resolved EELS and EDS analysis of HfO_xN_y gate dielectrics deposited by MOCVD using [(C₂H₅) ₂N]₄Hf with NO and O₂

Wu, X., Couillard, M., Lee, M. S., Chen, J. H., Botton, G. A., Landheer, D., Lu, Z. H., Ng, W. T. & Chao, T-S., 24 9月 2004, 於: Microscopy and Microanalysis. 10, SUPPL. 2, p. 606-607 2 p.

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Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs with RTA-Improved Crystallinity

Shen, C. H., Kuo, P. Y., Chung, C. C., Lee, S. Y. & Chao, T-S., 1 4月 2018, 於: IEEE Electron Device Letters. 39, 4, p. 512-515 4 p.

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4 引文斯高帕斯（Scopus）

Structure and thermal stability of MOCVD ZrO₂ films on Si (1 0 0)

Wu, X., Landheer, D., Graham, M. J., Chen, H. W., Huang, T. Y. & Chao, T-S., 1 4月 2003, 於: Journal of Crystal Growth. 250, 3-4, p. 479-485 7 p.

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28 引文斯高帕斯（Scopus）

Suppression of boron penetration by using inductive-coupling-nitrogen-plasma in stacked amorphous/polysilicon gate structure

Yang, W. L., Lin, C. J., Chao, T-S., Liu, D. G. & Lei, T. F., 19 6月 1997, 於: Electronics Letters. 33, 13, p. 1139-1140 2 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Suppression of boron penetration in BF ₂ ⁺ -implanted poly-Si gate

Chao, T-S., Chu, C. H., Wang, C. F., Kuai Junz, H. O., Lei, T. F. & Lee, C. L., 12月 1996, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 35, 12 A, p. 6003-6007 5 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Suppression of boron penetration in P⁺-poly-Si gate metal-oxide-semiconductor transistor using nitrogen implantation

Chao, T-S., Chien, C-H., Hao, C. P., Liaw, M. C., Chu, C. H., Chang, C. Y., Lei, T. F., Sun, W. T. & Hsu, C. H., 3月 1997, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 36, 3 SUPPL. B, p. 1364-1367 4 p.

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12 引文斯高帕斯（Scopus）

Suppression of boron penetration in P⁺-Poly-SiGe Gate P-channel metal-oxide-semiconductor field-effect transistor using NH₃-Nitrided and N₂O-grown gate oxides

Yang, W. L., Chao, T-S. & Lai, K. H., 11月 2004, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 43, 11 A, p. 7462-7463 2 p.

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1 引文斯高帕斯（Scopus）

Suppression of boron penetration in p⁺ polysilicon gate using Si-B diffusion source

Chao, T-S., Kuo, C. P., Lei, T. F., Chen, T. P., Huang, T. Y. & Chang, C. Y., 8 1月 1998, 於: Electronics Letters. 34, 1, p. 128-129 2 p.

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2 引文斯高帕斯（Scopus）

Suppression of boron penetration in pmos by using oxide gettering effect in poly-si gate

Lin, Y. H., Lee, C. L., Lei, T. F. & Chao, T-S., 2月 1995, 於: Japanese journal of applied physics. 34, 2S, p. 752-756 5 p.

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4 引文斯高帕斯（Scopus）

Suppression of interfacial reaction for HfO₂ on silicon by pre-CF₄ plasma treatment

Lai, C. S., Wu, W. C., Chao, T-S., Chen, J. H., Wang, J. C., Tay, L. L. & Rowell, N., 25 8月 2006, 於: Applied Physics Letters. 89, 7, 072904.

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39 引文斯高帕斯（Scopus）

Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure

Kuo, P. Y., Chao, T-S. & Lei, T. F., 1 9月 2004, 於: IEEE Electron Device Letters. 25, 9, p. 634-636 3 p.

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12 引文斯高帕斯（Scopus）

Susceptor coupling for the uniformity and dopant activation efficiency in implanted Si under fixed-frequency microwave anneal

Lee, Y. J., Hsueh, F. K., Current, M. I., Wu, C. Y. & Chao, T-S., 1 2月 2012, 於: IEEE Electron Device Letters. 33, 2, p. 248-250 3 p., 6105514.

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11 引文斯高帕斯（Scopus）

Switching characteristics in Cu:SiO₂ by chemical soak methods for resistive random access memory (ReRAM)

Chin, F. T., Lin, Y. H., Yang, W. L., Liao, C. H., Lin, L. M., Hsiao, Y. P. & Chao, T-S., 1 1月 2015, 於: Solid-State Electronics. 103, p. 190-194 5 p.

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7 引文斯高帕斯（Scopus）

Symmetric vertical-channel nickel-salicided poly-Si thin-film transistors with self-aligned oxide overetching structures

Wu, Y. H., Kuo, P. Y., Lu, Y. H., Chen, Y. H., Chiang, T. Y., Wang, K. T., Yen, L. C. & Chao, T-S., 1 7月 2011, 於: IEEE Transactions on Electron Devices. 58, 7, p. 2008-2013 6 p., 5765490.

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4 引文斯高帕斯（Scopus）

Systematical study of reliability issues in plasma-nitrided and thermally nitrided oxides for advanced dual-gate oxide p-channel metal-oxide-semiconductor field-effect transistors

Lo, W. C., Wu, S. Y., Chang, S. J., Chiang, M. C., Lin, C. Y., Chao, T-S. & Chang, C. Y., 8 3月 2007, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 46, 3 A, p. 1124-1128 5 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Temperature dependence of electron mobility on strained nMOSFETs fabricated by strain-gate engineering

Chang, T. S., Lu, T. Y. & Chao, T-S., 8 5月 2012, 於: IEEE Electron Device Letters. 33, 7, p. 931-933 3 p., 6193407.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

The characteristics of n- and p-channel poly-si thin-film transistors with fully Ni-salicided S/D and gate structure

Kuo, P. Y., Huang, Y. S., Lue, Y. H., Chao, T-S. & Lei, T. F., 1 1月 2010, 於: Journal of the Electrochemical Society. 157, 1

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

The effects of dielectric type and thickness on the characteristics of dynamic threshold metal oxide semiconductor transistors

Lee, Y. J., Chao, T-S. & Huang, T. Y., 9月 2003, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 42, 9 A, p. 5405-5409 5 p.

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4 引文斯高帕斯（Scopus）

The effects of super-steep-retrograde indium channel profile on deep submicron n-channel metal-oxide-semiconductor field-effect transistor

Chen, C., Chang, S. J., Chou, J. W., Lin, T., Yeh, W. K., Chang, C. Y., Luo, W. Z., Lee, Y. J., Chao, T-S. & Huang, T. Y., 1月 2001, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 40, 1, p. 75-79 5 p.

研究成果: Article › 同行評審

The impact of deep Ni salicidation and NH₃ plasma treatment on nano-SOI FinFETs

You, H. C., Kuo, P. Y., Ko, F-H., Chao, T-S. & Lei, T. F., 1 12月 2006, 於: IEEE Electron Device Letters. 27, 10, p. 799-801 3 p.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

The refractive index of InP and its oxide measured by multiple-angle incident ellipsometry

Chao, T-S., Lee, C. L. & Lei, T. F., 1 10月 1993, 於: Journal of Materials Science Letters. 12, 10, p. 721-723 3 p.

研究成果: Article › 同行評審

The zero-temperature-coefficient point modeling of DTMOS in CMOS Integration

Wang, K. T., Lin, W. C. & Chao, T-S., 1 10月 2010, 於: IEEE Electron Device Letters. 31, 10, p. 1071-1073 3 p., 5540257.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Thickness determination of poly-Si/poly-oxide/poly-Si/SiO₂/Si structure by ellipsometer

Chao, T-S., Lee, C. L. & Lei, T. F., 1 1月 1993, 於: Electronics Letters. 29, 13, p. 1157-1159 3 p.

研究成果: Article › 同行評審

Thin Polyoxide on the Top of Poly-Si Gate to Suppress Boron Penetration for pMOS

Lin, Y. H., Lee, C. L., Lei, T. F. & Chao, T-S., 1 1月 1995, 於: IEEE Electron Device Letters. 16, 5, p. 164-165 2 p.

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8 引文斯高帕斯（Scopus）

Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension

Hsien, L. J., Chan, Y. L., Chao, T-S., Jiang, Y. L. & Kung, C. Y., 7月 2002, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 41, 7 A, p. 4519-4520 2 p.

研究成果: Article › 同行評審

Ultrathin Sub-5-nm Hf_1-xZr_xO₂for a Stacked Gate-all-Around Nanowire Ferroelectric FET with Internal Metal Gate

Lee, S. Y., Lee, C. C., Kuo, Y. S., Li, S. W. & Chao, T. S., 2月 2021, 於: IEEE Journal of the Electron Devices Society. 9, p. 236-241 6 p., 9344700.

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6 引文斯高帕斯（Scopus）

Ultrathin zirconium silicate films deposited on Si(100) using Zr(Oⁱ-Pr)₂(thd)₂, Si(O^t-Bu)₂(thd)₂, and nitric oxide

Chen, H. W., Huang, T. Y., Landheer, D., Wu, X., Moisa, S., Sproule, G. I., Kim, J. K., Lennard, W. N. & Chao, T-S., 1 7月 2003, 於: Journal of the Electrochemical Society. 150, 7

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8 引文斯高帕斯（Scopus）

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