Tien-Sheng Chao

Article

High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications

Sung, P. J., Cho, T. C., Hou, F. J., Hsueh, F. K., Chung, S. T., Lee, Y. J., Current, M. I. & Chao, T-S., 1 5月 2017, 於: IEEE Transactions on Electron Devices. 64, 5, p. 2054-2060 7 p., 7885526.

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7 引文斯高帕斯（Scopus）

High-program/erase-speed SONOS with in situ silicon nanocrystals

Chiang, T. Y., Chao, T-S., Wu Yi-Hong, Y. H. & Yang, W. L., 11 9月 2008, 於: IEEE Electron Device Letters. 29, 10, p. 1148-1151 4 p.

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22 引文斯高帕斯（Scopus）

High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices

Yang, W. L., Chao, T-S., Cheng, C. M., Pan, T. M. & Lei, T. F., 1 7月 2001, 於: IEEE Transactions on Electron Devices. 48, 7, p. 1304-1309 6 p.

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9 引文斯高帕斯（Scopus）

High quality interpoly-oxynitride grown by NH₃ nitridation and N₂O RTA treatment

Pan, T. M., Lei, T. F., Yang, W. L., Cheng, C. M. & Chao, T-S., 1 2月 2001, 於: IEEE Electron Device Letters. 22, 2, p. 68-70 3 p.

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9 引文斯高帕斯（Scopus）

High-quality native-oxide-free ultra-thin oxide grown by in-situ HF-vapour treatment

Chen, C. L., Chao, T-S., Lai, C. S. & Huang, T. Y., 25 5月 2000, 於: Electronics Letters. 36, 11, p. 981-983 3 p.

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2 引文斯高帕斯（Scopus）

High quality ultrathin CoTiO₃ high-k gate dielectrics

Pan, T. M., Lei, T. F., Chao, T-S., Chang, K. L. & Hsieh, K. C., 1 9月 2000, 於: Electrochemical and Solid-State Letters. 3, 9, p. 433-434 2 p.

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14 引文斯高帕斯（Scopus）

High-reliability dynamic-threshold source-side injection for 2-bit/cell with MLC operation of wrapped select-gate SONOS in NOR-type flash memory

Wang, K. T., Chao, T-S., Wu, W. C., Yang, W. L., Lee, C. H., Hsieh, T. M., Liou, J. C., Wang, S. D., Chen, T. P., Chen, C. H., Lin, C. H. & Chen, H. H., 1 9月 2010, 於: IEEE Transactions on Electron Devices. 57, 9, p. 2335-2338 4 p., 5510121.

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3 引文斯高帕斯（Scopus）

High-speed multilevel wrapped-select-gate SONOS memory using a novel dynamic

Wang, K. T., Chao, T-S., Wu, W. C., Chiang, T. Y., Wu, Y. H., Yang, W. L., Lee, C. H., Hsieh, T. M., Liou, J. C., Wang, S. D., Chen, T. P., Chen, C. H., Lin, C. H. & Chen, H. H., 30 4月 2009, 於: IEEE Electron Device Letters. 30, 6, p. 659-661 3 p.

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2 引文斯高帕斯（Scopus）

High tensile stress with minimal dopant diffusion by low temperature microwave anneal

Lee, Y. J., Lu, Y. L., Mu, Z. C., Hsueh, F. K., Chao, T-S. & Wu, C. Y., 16 3月 2011, 於: Electrochemical and Solid-State Letters. 14, 5

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1 引文斯高帕斯（Scopus）

High-Voltage and High-Temperature Applications of DTMOS With Reverse Schottky Barrier on Substrate Contacts

Chao, T-S., Lee, Y. J. & Huang, T. Y., 1 2月 2004, 於: IEEE Electron Device Letters. 25, 2, p. 86-88 3 p.

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2 引文斯高帕斯（Scopus）

High voltage applications and NBTI effects of DT-pMOSFETS with reverse Schottky substrate contacts

Lee, Y. J., Chao, T-S. & Huang, T. Y., 1 7月 2005, 於: Microelectronics Reliability. 45, 7-8, p. 1119-1123 5 p.

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High-κEu₂O₃ and Y₂O₃ poly-Si thin-film transistor nonvolatile memory devices

Pan, T. M., Yen, L. C., Huang, S. H., Lo, C. T. & Chao, T-S., 15 7月 2013, 於: IEEE Transactions on Electron Devices. 60, 7, p. 2251-2255 5 p., 6523940.

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6 引文斯高帕斯（Scopus）

High-κ material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications

Ma, M. W., Chao, T-S., Kao, K. H., Huang, J. S. & Lei, T. F., 15 11月 2006, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 11, p. 8656-8658 3 p.

研究成果: Article › 同行評審

Hot carrier degradations of dynamic threshold silicon on insulator p-type metal-oxide-semiconductor field effect transistors

Chao, T. S., Lee, Y. J., Huang, C. Y., Lin, H. C., Li, Y-M. & Huang, T. Y., 4月 2004, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 43, 4 A, p. 1300-1304 5 p.

研究成果: Article › 同行評審

Hydrogen instability induced by postannealing on poly-Si TFTs

Liao, C. C., Lin, M. C. & Chao, T-S., 24 4月 2012, 於: IEEE Transactions on Electron Devices. 59, 6, p. 1807-1809 3 p., 6185651.

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2 引文斯高帕斯（Scopus）

Hysteresis-Free Gate-All-Around Stacked Poly-Si Nanosheet Channel Ferroelectric Hf_xZr_1-xO₂Negative Capacitance FETs With Internal Metal Gate and NH₃Plasma Nitridation

Lee, C. C., Hsieh, D. R., Li, S. W., Kuo, Y. S. & Chao, T. S., 1 3月 2022, 於: IEEE Transactions on Electron Devices. 69, 3, p. 1512-1518 7 p.

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Impact of channel dangling bonds on reliability characteristics of Flash memory on poly-Si thin films

Lin, Y. H., Chien, C-H., Chou, T. H., Chao, T-S. & Lei, T. F., 1 4月 2007, 於: IEEE Electron Device Letters. 28, 4, p. 267-269 3 p.

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8 引文斯高帕斯（Scopus）

Impact of Crystallization Method on Poly-Si Tunnel FETs

Chen, Y. H., Ma, W. C. Y., Lin, J. Y., Lin, C. Y., Hsu, P. Y., Huang, C. Y. & Chao, T-S., 1 10月 2015, 於: IEEE Electron Device Letters. 36, 10, p. 1060-1062 3 p., 7194770.

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13 引文斯高帕斯（Scopus）

Impact of High-K Offset Spacer in 65-nm Node SOI Devices

Ma, M. W., Lei, T. F., Wu, C. H., Wang, S. J., Yang, T. Y., Kao, K. H., Wu, W. C. & Chao, T-S., 7 3月 2007, 於: IEEE Electron Device Letters. 28, 3, p. 238-241 4 p.

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25 引文斯高帕斯（Scopus）

Impact of nitrogen and/or fluorine implantation on deep-submicron Co-salicide process

Chang, T. Y., Lei, T. F., Chao, T-S., Chen, S. W., Kao, L. M., Chen, S. K., Tuan, A. & Su, T. P., 1 8月 2002, 於: Solid-State Electronics. 46, 8, p. 1097-1101 5 p.

研究成果: Article › 同行評審

Impact of strain layer on gate leakage and interface-state for nMOSFETs fabricated by stress-memorization technique

Liao, C. C., Lin, M. C., Chiang, T. Y. & Chao, T-S., 24 1月 2011, 於: Electrochemical and Solid-State Letters. 14, 1

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Impacts of a buffer layer and hydrogen-annealed wafers on the performance of strained-channel nMOSFETs with SiN-capping layer

Tsai, T. I., Lin, H-C., Lee, Y. J., Chen, K. S., Wang, J., Hsueh, F. K., Chao, T-S. & Huang, T. Y., 1 10月 2008, 於: Solid-State Electronics. 52, 10, p. 1518-1524 7 p.

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1 引文斯高帕斯（Scopus）

Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-κ LTPS-TFT

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Yang, T. Y., Kao, K. H., Chao, T-S. & Lei, T. F., 1 2月 2008, 於: IEEE Electron Device Letters. 29, 2, p. 168-170 3 p.

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6 引文斯高帕斯（Scopus）

Impacts of gate structure on dynamic threshold SOI nMOSFETs

Lo, W. C., Chang, S. J., Chang, C. Y. & Chao, T-S., 1 8月 2002, 於: IEEE Electron Device Letters. 23, 8, p. 497-499 3 p.

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17 引文斯高帕斯（Scopus）

Impacts of multiple strain-gate engineering on a zero-temperature- coefficient point

Chang, T. S., Lu, T. Y. & Chao, T-S., 5 4月 2013, 於: IEEE Electron Device Letters. 34, 4, p. 481-486 6 p., 6484132.

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1 引文斯高帕斯（Scopus）

Impacts of N ₂ and NH ₃ plasma surface treatments on high-performance LTPS-TFT with high-κ gate dielectric

Ma, M. W., Chao, T-S., Chiang, T. Y., Wu, W. C. & Lei, T. F., 18 9月 2008, 於: IEEE Electron Device Letters. 29, 11, p. 1236-1238 3 p.

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11 引文斯高帕斯（Scopus）

Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs

Kumar, M. P. V., Hu, C. Y., Kao, K. H., Lee, Y. J. & Chao, T-S., 7 9月 2015, 於: IEEE Transactions on Electron Devices. 62, 11, p. 3541-3546 6 p., 7244201.

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29 引文斯高帕斯（Scopus）

Impacts of the underlying insulating layers on the MILC growth length and electrical characteristics

Liao, C. C., Lin, M. C., Liu, S. X. & Chao, T-S., 1 2月 2012, 於: IEEE Electron Device Letters. 33, 2, p. 239-241 3 p., 6101550.

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1 引文斯高帕斯（Scopus）

Improved flash cell performance by N₂O annealing of interpoly oxide

Jong, F. C., Huang, T. Y., Chao, T-S., Lin, H-C., Leu, L. Y., Young, K., Lin, C. H. & Chiu, K. Y., 1 7月 1997, 於: IEEE Electron Device Letters. 18, 7, p. 343-345 3 p.

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9 引文斯高帕斯（Scopus）

Improved low temperature characteristics of p-channel MOSFETs with Si _1-xGe _x raised source and drain

Huang, H. J., Chen, K. M., Huang, T. Y., Chao, T-S., Huang, G. W., Chien, C-H. & Chang, C. Y., 1 8月 2001, 於: IEEE Transactions on Electron Devices. 48, 8, p. 1627-1632 6 p., 936576.

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7 引文斯高帕斯（Scopus）

Improved rear-side passivation by atomic layer deposition A ₂ O ₃ /SiN _x stack layers for high V _OC industrial p-type silicon solar cells

Lin, J. W., Chen, Y. Y., Gan, J. Y., Hseih, W. P., Du, C. H. & Chao, T-S., 3 9月 2013, 於: IEEE Electron Device Letters. 34, 9, p. 1163-1165 3 p., 6558507.

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2 引文斯高帕斯（Scopus）

Improvement in pH sensitivity of low-temperature polycrystalline-silicon thin-film transistor sensors using H₂ sintering

Yen, L. C., Tang, M. T., Chang, F. Y., Pan, T. M., Chao, T-S. & Lee, C. H., 25 2月 2014, 於: Sensors (Switzerland). 14, 3, p. 3825-3832 8 p.

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5 引文斯高帕斯（Scopus）

Improvement of junction leakage of nickel silicided junction by a Ti-capping layer

Hou, T-H., Lei, T. F. & Chao, T-S., 1 11月 1999, 於: IEEE Electron Device Letters. 20, 11, p. 572-573 2 p.

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55 引文斯高帕斯（Scopus）

Improvement of low-temperature gate dielectric formed in N ₂ O plasma by an additional CF ₄ pretreatment process

Chang, T. Y., Lei, T. F., Chao, T-S., Wen, H. C. & Chen, H. W., 1 7月 2002, 於: IEEE Electron Device Letters. 23, 7, p. 389-391 3 p.

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5 引文斯高帕斯（Scopus）

Improvement of polysilicon oxide by growing on polished polysilicon film

Lei, T. F., Cheng, J. Y., Shiau, S. Y., Chao, T-S. & Lai, C. S., 1 6月 1997, 於: IEEE Electron Device Letters. 18, 6, p. 270-271 2 p.

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16 引文斯高帕斯（Scopus）

Improvement of polysilicon oxide integrity using NF₃-annealing

Yang, W. L., Shieh, M. S., Chen, Y. M., Chao, T-S., Liu, D. G. & Lei, T. F., 15 6月 2000, 於: Japanese Journal of Applied Physics, Part 2: Letters. 39, 6 B, p. L562-L563

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4 引文斯高帕斯（Scopus）

Improvement of reliability of metal-oxide semiconductor field-effect transistors with N₂O nitrided gate oxide and N₂O polysilicon gate reoxidation

Lai, C. S., Chao, T-S., Lei, T. F., Lee, C. L., Huang, T. Y. & Chang, C. Y., 10月 1998, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 37, 10, p. 5507-5509 3 p.

研究成果: Article › 同行評審

Improvement of thin oxides thermally grown on the reactive-ion-etched silicon substrates

Ueng, S. Y., Wang, P. W., Kang, T. K., Chao, T-S., Chen, W. H., Dai, B. T. & Cheng, H. C., 5月 1995, 於: Japanese journal of applied physics. 34, 5R, p. 2266-2271 6 p.

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2 引文斯高帕斯（Scopus）

Improvement of ultra-thin 3.3 nm thick oxide for Co-salicide process using NF ₃ annealed poly-gate

Chang, T. Y., Lei, T. F., Chao, T-S., Huang, C. T., Chen, S. K., Tuan, A. & Chou, S., 1999, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 38, 4 B, p. 2243-2246 4 p.

研究成果: Article › 同行評審

Improvement on performance and reliability of TaN/HfO₂ LTPS-TFTs with fluorine implantation

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Yang, T. Y., Kao, K. H., Chao, T-S. & Lei, T. F., 1 3月 2008, 於: Solid-State Electronics. 52, 3, p. 342-347 6 p.

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2 引文斯高帕斯（Scopus）

Improving electrical characteristics of High-k NiTiO dielectric with nitrogen ion implantation

Yang, W. L., Chao, T-S., Chen, S. C., Yang, C. H. & Peng, W. C., 7 9月 2006, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 9 A, p. 6902-6904 3 p.

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2 引文斯高帕斯（Scopus）

Improving radiation hardness of EEPROM/flash cell by N ₂ O annealing

Huang, T. Y., Jong, F. C., Chao, T-S., Lin, H-C., Leu, L. Y., Young, K., Lin, C. H. & Chiu, K. Y., 1 7月 1998, 於: IEEE Electron Device Letters. 19, 7, p. 256-258 3 p.

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12 引文斯高帕斯（Scopus）

Improving the Electrical Performance of a Quantum Well FET with a Shell Doping Profile by Heterojunction Optimization

Kumar, M. P. V., Hu, C. Y., Walke, A. M., Kao, K. H. & Chao, T-S., 1 9月 2017, 於: IEEE Transactions on Electron Devices. 64, 9, p. 3563-3568 6 p., 7990547.

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5 引文斯高帕斯（Scopus）

Inductive-coupling-nitrogen-plasma process for suppression of boron penetration in BF₂⁺-implanted polycrystalline silicon gate

Chao, T-S. & Chu, C. H., 6 1月 1997, 於: Applied Physics Letters. 70, 1, p. 55-56 2 p.

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3 引文斯高帕斯（Scopus）

Inhibition of bird's beak in LOCOS by new buffer N₂O oxide

Chao, T-S., Cheng, J. Y. & Lei, T. F., 16 2月 1995, 於: Electronics Letters. 31, 4, p. 323-324 2 p.

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1 引文斯高帕斯（Scopus）

Investigation of Channel Doping Concentration and Reverse Boron Penetration on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode FETs

Hsieh, D. R., Chan, Y. D., Kuo, P. Y. & Chao, T-S., 7 2月 2018, 於: IEEE Journal of the Electron Devices Society. 6, 1, p. 314-319 6 p.

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4 引文斯高帕斯（Scopus）

Investigation of Nitrous Oxide Nitridation Temperatures on P-Type Pi-Gate Poly-Si Junctionless Accumulation Mode TFTs

Hsieh, D. R., Lin, K. C. & Chao, T-S., 1 1月 2019, 於: IEEE Journal of the Electron Devices Society. 7, p. 268-275 8 p., 8630465.

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2 引文斯高帕斯（Scopus）

Investigation of Two Bits with Multistate Antifuse on nMOS Poly-Silicon Junctionless GAA OTP

Chang, C. F., Shen, C. H., Hsieh, D. R., Lu, Z. H., Lin, C. C. & Chao, T. S., 1 12月 2021, 於: IEEE Transactions on Electron Devices. 68, 12, p. 6118-6123 6 p.

研究成果: Article › 同行評審

Ion-bombarded and plasma-passivated charge storage layer for SONOS-type nonvolatile memory

Liu, S. H., Wu, C. C., Yang, W. L., Lin, Y. H. & Chao, T-S., 1 1月 2014, 於: IEEE Transactions on Electron Devices. 61, 9, p. 3179-3185 7 p., 6872548.

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2 引文斯高帕斯（Scopus）

Junctionless FETs with a Fin Body for Multi-V _TH and Dynamic Threshold Operation

Kumar, M. P. V., Lin, J. Y., Kao, K. H. & Chao, T-S., 1 8月 2018, 於: IEEE Transactions on Electron Devices. 65, 8, p. 3535-3542 8 p., 8399532.

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7 引文斯高帕斯（Scopus）

趙 天生

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趙天生