Tien-Sheng Chao

Article

A carbon nanotube field effect transistor with tunable conduction-type by electrostatic effects

Chen, B. H., Wei, J. H., Lo, P. Y., Wang, H. H., Lai, M. J., Tsai, M. J., Chao, T-S., Lin, H-C. & Huang, T. Y., 1 7月 2006, 於: Solid-State Electronics. 50, 7-8, p. 1341-1348 8 p.

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13 引文斯高帕斯（Scopus）

A comprehensive study of hot carrier stress-induced drain leakage current degradation in thin-oxide n-MOSFET's

Wang, T-H., Chiang, L. P., Zous, N. K., Hsu, C. F., Huang, L. Y. & Chao, T-S., 1 12月 1999, 於: IEEE Transactions on Electron Devices. 46, 9, p. 1877-1882 6 p.

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41 引文斯高帕斯（Scopus）

A domain partition approach to parallel adaptive simulation of dynamic threshold voltage MOSFET

Li, Y-M., Chao, T. S. & Sze, S. M., 1 8月 2002, 於: Computer Physics Communications. 147, 1-2, p. 697-701 5 p.

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15 引文斯高帕斯（Scopus）

Advanced Cu chemical displacement technique for SiO₂-based electrochemical metallization ReRAM application

Chin, F. T., Lin, Y. H., You, H. C., Yang, W. L., Lin, L. M., Hsiao, Y. P., Ko, C. M. & Chao, T-S., 1 1月 2014, 於: Nanoscale Research Letters. 9, 1

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9 引文斯高帕斯（Scopus）

A Harmonic Radar Tag with High Detection Range Utilizing Ge FinFETs CMOS Technology

Hsieh, C. H., Hong, T. C., Yang, C. Y., Chen, Y. H., Yu, X. R., Lu, W. H., Chuang, R. W., Tsai, Z. M., Lee, Y. J., Li, Y. M., Wu, W. F., Chao, T. S., Samukawa, S., Wang, Y. H., Yeh, W-K. & Tarng, J. H., 2022, (Accepted/In press) 於: Ieee Electron Device Letters. p. 1 1 p.

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Al-SiO₂-Y₂O₃-SiO₂-poly-si thin-film transistor nonvolatile memory incorporating a Y₂O ₃ charge trapping layer

Pan, T. M., Yen, L. C., Mondal, S., Lo, C. T. & Chao, T-S., 26 7月 2013, 於: ECS Solid State Letters. 2, 10

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2 引文斯高帕斯（Scopus）

Amorphous-layer regrowth and activation of P and as implanted Si by low-temperature microwave annealing

Hsueh, F. K., Lee, Y. J., Lin, K. L., Current, M. I., Wu, C. Y. & Chao, T-S., 1 7月 2011, 於: IEEE Transactions on Electron Devices. 58, 7, p. 2088-2093 6 p., 5746514.

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20 引文斯高帕斯（Scopus）

An Exothermic Phenomenon of Silicon Oxidation by N₂O

Chao, T-S., Chen, W. H., Sun, S. C. & Chang, H. Y., 1 1月 1993, 於: Journal of the Electrochemical Society. 140, 11, p. L160-L161

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4 引文斯高帕斯（Scopus）

Anomalous crossover in Vth roll-off for indium-doped nMOSFETs

Chang, S. J., Chang, C. Y., Chen, C., Chou, J. W., Chao, T-S. & Huang, T. Y., 9月 2000, 於: IEEE Electron Device Letters. 21, 9, p. 457-459 3 p.

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6 引文斯高帕斯（Scopus）

A novel ion-bombarded and plasma-passivated charge storage layer for SONOS-type nonvolatile memory

Liu, S. H., Yang, W. L., Wu, C. C. & Chao, T-S., 29 8月 2012, 於: IEEE Electron Device Letters. 33, 10, p. 1393-1395 3 p., 6280616.

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10 引文斯高帕斯（Scopus）

A novel parallel approach for quantum effect simulation in semiconductor devices

Li, Y-M., Chao, T. S. & Sze, S. M., 1 1月 2003, 於: International Journal of Modelling and Simulation. 23, 2, p. 94-102 9 p.

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11 引文斯高帕斯（Scopus）

A novel planarization of oxide-filled shallow-trench isolation

Cheng, J. Y., Lei, T. F., Chao, T-S., Yen, D. L. W., Jin, B. J. & Lin, C. J., 1 1月 1997, 於: Journal of the Electrochemical Society. 144, 1, p. 315-320 6 p.

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11 引文斯高帕斯（Scopus）

A novel p-n-diode structure of SONOS-type TFT NVM with embedded silicon nanocrystals

Chiang, T. Y., Ma, W. C. Y., Wu, Y. H., Wang, K. T. & Chao, T-S., 1 11月 2010, 於: IEEE Electron Device Letters. 31, 11, p. 1239-1241 3 p., 5565385.

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7 引文斯高帕斯（Scopus）

A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

Lin, H-C., Lin, R., Wu, W. F., Yang, R. P., Tsai, M. S., Chao, T-S. & Huang, T. Y., 1 1月 1998, 於: IEEE Electron Device Letters. 19, 1, p. 26-28 3 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

A novel shallow trench isolation technique

Cheng, J. Y., Lei, T. F. & Chao, T-S., 3月 1997, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 36, 3 SUPPL. B, p. 1319-1324 6 p.

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15 引文斯高帕斯（Scopus）

A novel Si-B diffusion source for p⁺-poly-Si gate

Chao, T-S., Kuo, C. P., Chen, T. P. & Lei, T. F., 1 1月 1999, 於: Journal of the Electrochemical Society. 146, 10, p. 3852-3855 4 p.

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A One-Step Single-Cleaning Solution for CMOS Processes

Chao, T-S., Yeh, C. H., Pan, T. M., Lei, T. F. & Li, Y. H., 1 9月 2003, 於: Journal of the Electrochemical Society. 150, 9

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7 引文斯高帕斯（Scopus）

A practical implementation of parallel dynamic load balancing for adaptive computing in VLSI device simulation

Li, Y-M., Sze, S. M. & Chao, T-S., 8月 2002, 於: Engineering with Computers. 18, 2, p. 124-137 14 p.

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98 引文斯高帕斯（Scopus）

A simple method for sub-100 nm pattern generation with I-line double-patterning technique

Tsai, T. I., Lin, H-C., Jian, M. F., Huang, T. Y. & Chao, T-S., 1 5月 2010, 於: Microelectronics Reliability. 50, 5, p. 584-588 5 p.

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1 引文斯高帕斯（Scopus）

A study of interface trap generation by fowler-nordheim and substrate-hot-carrier stresses for 4-nm thick gate oxides

Shiue, J. H., Lee, J. Y. M. & Chao, T-S., 1 12月 1999, 於: IEEE Transactions on Electron Devices. 46, 8, p. 1705-1710 6 p.

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25 引文斯高帕斯（Scopus）

A study of the interfacial layer of Al and Al(1% Si)Si contacts using a zero-layer ellipsometry model

Chao, T-S., Lee, C. L. & Lei, T. F., 1 1月 1992, 於: Solid State Electronics. 35, 11, p. 1579-1584 6 p.

研究成果: Article › 同行評審

A study on the radiation hardness of flash cell with horn-shaped floating-gate

Huang, T. Y., Jong, F. C., Chao, T-S., Lin, H-C., Leu, L. Y., Young, K., Lin, C. H. & Chiu, K. Y., 9月 1997, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 36, 9 A, p. 5459-5463 5 p.

研究成果: Article › 同行評審

Benefit of NMOS by compressive SiN as stress memorization technique and its mechanism

Liao, C. C., Chiang, T. Y., Lin, M. C. & Chao, T-S., 1 4月 2010, 於: IEEE Electron Device Letters. 31, 4, p. 281-283 3 p., 11.

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10 引文斯高帕斯（Scopus）

Carrier transportation mechanism of the TaN/HfO₂/IL/Si structure with silicon surface fluorine implantation

Wu, W. C., Lai, C. S., Wang, T. M., Wang, J. C., Hsu, C. W., Ma, M. W., Lo, W. C. & Chao, T-S., 1 7月 2008, 於: IEEE Transactions on Electron Devices. 55, 7, p. 1639-1646 8 p.

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27 引文斯高帕斯（Scopus）

Channel film thickness effect of low-temperature polycrystalline-silicon thin-film transistors

Ma, W. C. Y., Chiang, T. Y., Yeh, C. R., Chao, T-S. & Lei, T. F., 1 4月 2011, 於: IEEE Transactions on Electron Devices. 58, 4, p. 1268-1272 5 p., 5723733.

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10 引文斯高帕斯（Scopus）

Channel thickness effect on high-frequency performance of poly-Si thin-film transistors

Chen, K. M., Tsai, T. I., Lin, T. Y., Lin, H-C., Chao, T-S., Huang, G. W. & Huang, T. Y., 12 7月 2013, 於: IEEE Electron Device Letters. 34, 8, p. 1020-1022 3 p., 6553156.

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12 引文斯高帕斯（Scopus）

Characteristics of fluorine implantation for HfO₂ gate dielectrics with high-temperature postdeposition annealing

Lai, C. S., Wu, W. C., Wang, J. C. & Chao, T-S., 25 4月 2006, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 45, 4 B, p. 2893-2897 5 p.

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9 引文斯高帕斯（Scopus）

Characteristics of HfO ₂ /Poly-Si interfacial layer on CMOS LTPS-TFTs with HfO ₂ gate dielectric and O ₂ plasma surface treatment

Ma, M. W., Chiang, T. Y., Wu, W. C., Chao, T-S. & Lei, T. F., 10 12月 2008, 於: IEEE Transactions on Electron Devices. 55, 12, p. 3489-3493 5 p.

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17 引文斯高帕斯（Scopus）

Characteristics of in_0.7Ga_0.3as MOS capacitors obtained using hydrochloric acid treatment, ammonium sulfide passivation, methanol treatment, and forming gas annealing

Chung, S. T., Huang, Y. C., Fu, Y. C., Lee, Y. J. & Chao, T-S., 1 1月 2019, 於: ECS Journal of Solid State Science and Technology. 8, 9, p. P457-P463

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1 引文斯高帕斯（Scopus）

Characteristics of In_0.7Ga_0.3As MOS Capacitors with Sulfur and Hydrazine Pretreatments

Lee, Y. J., Chung, S. T., Su, C. J., Cho, T. C. & Chao, T. S., 9月 2021, 於: ECS Journal of Solid State Science and Technology. 10, 9, 095002.

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Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-κ gate dielectric

Ma, M. W., Chen, C. Y., Su, C. J., Wu, W. C., Wu, Y. H., Kao, K. H., Chao, T-S. & Lei, T. F., 1 2月 2008, 於: IEEE Electron Device Letters. 29, 2, p. 171-173 3 p.

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19 引文斯高帕斯（Scopus）

Characteristics of Poly-Si Junctionless FinFETs with HfZrO Using Forming Gas Annealing

Chung, S. T., Lee, Y. J. & Chao, T. S., 1 1月 2020, 於: IEEE Transactions on Nanotechnology. 19, p. 390-396 7 p., 9091928.

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Characteristics of polysilicon oxides combining N ₂O nitridation and CMP processes

Lei, T. F., Chen, J. H., Wang, M. F. & Chao, T-S., 1 8月 2000, 於: IEEE Transactions on Electron Devices. 47, 8, p. 1545-1552 8 p.

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1 引文斯高帕斯（Scopus）

Characteristics of self-aligned Si/Ge T-gate poly-si thin-film transistors with high on/off current ratio

Kuo, P. Y., Chao, T-S., Hsieh, P. S. & Lei, T. F., 1 5月 2007, 於: IEEE Transactions on Electron Devices. 54, 5, p. 1171-1176 6 p.

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10 引文斯高帕斯（Scopus）

Characteristics of SONOS-Ttpe flash memory with in situ embedded silicon nanocrystals

Chiang, T. Y., Wu, Y. H., Ma, W. C. Y., Kuo, P. Y., Wang, K. T., Liao, C. C., Yeh, C. R., Yang, W. L. & Chao, T-S., 1 8月 2010, 於: IEEE Transactions on Electron Devices. 57, 8, p. 1895-1902 8 p., 5497125.

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11 引文斯高帕斯（Scopus）

Characteristics of TEOS polysilicon oxides: Improvement by CMP and high temperature RTA N₂/N₂O annealing

Chen, J. H., Lei, T. F., Chen, J. H. & Chao, T-S., 1 11月 2000, 於: Journal of the Electrochemical Society. 147, 11, p. 4282-4288 7 p.

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9 引文斯高帕斯（Scopus）

Characterization of C F₄ -plasma fluorinated Hf O₂ gate dielectrics with TaN metal gate

Lai, C. S., Wu, W. C., Wang, J. C. & Chao, T-S., 4 7月 2005, 於: Applied Physics Letters. 86, 22, p. 1-3 3 p., 222905.

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36 引文斯高帕斯（Scopus）

Characterization of enhanced stress memorization technique on nMOSFETs by multiple strain-gate engineering

Lu, T. Y., Chang, T. S., Huang, S. A. & Chao, T-S., 1 4月 2011, 於: IEEE Transactions on Electron Devices. 58, 4, p. 1023-1028 6 p., 5723734.

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4 引文斯高帕斯（Scopus）

Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films

Lei, T. F., Cheng, J. Y., Shiau, S. Y., Chao, T-S. & Lai, C. S., 1 12月 1998, 於: IEEE Transactions on Electron Devices. 45, 4, p. 912-917 6 p., 662802.

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20 引文斯高帕斯（Scopus）

Characterization of thin ZrO₂ films deposited using Zr(Oⁱ-Pr)₂(thd)₂ and O₂ on Si(100)

Chen, H. W., Landheer, D., Wu, X., Moisa, S., Sproule, G. I., Chao, T-S. & Huang, T. Y., 1 5月 2002, 於: Journal of Vacuum Science and Technology, Part A: Vacuum, Surfaces and Films. 20, 3, p. 1145-1148 4 p.

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13 引文斯高帕斯（Scopus）

Characterization of ultra-thin Ni silicide film by two-step low temperature microwave anneal

Wu, C. T., Lee, Y. J., Hsueh, F. K., Sung, P. J., Cho, T. C., Current, M. I. & Chao, T-S., 1 1月 2014, 於: ECS Journal of Solid State Science and Technology. 3, 5

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4 引文斯高帕斯（Scopus）

Characterized of ultrathin oxynitride (18-21 Å) gate dielectrics by NH ₃ nitridation and N ₂O RTA treatment

Pan, T. M., Lei, T. F., Wen, H. C. & Chao, T-S., 1 5月 2001, 於: IEEE Transactions on Electron Devices. 48, 5, p. 907-912 6 p.

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16 引文斯高帕斯（Scopus）

CMOS-Compatible Fabrication of Low-Power Ferroelectric Tunnel Junction for Neural Network Applications

Kuo, Y. S., Lee, S. Y., Lee, C. C., Li, S. W. & Chao, T-S., 2月 2021, 於: IEEE Transactions on Electron Devices. 68, 2, p. 879-884 6 p., 9316796.

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9 引文斯高帕斯（Scopus）

Combined effects of nitrogen implantation at S/D extension and N ₂O oxide on 0.18 μm N- and P-metal oxide field effect transistors (MOSFETs)

Chao, T-S., Chang, S. J., Chien, C-H., Lin, H-C., Huang, T. Y. & Chang, C. Y., 1 12月 1999, 於: Japanese Journal of Applied Physics, Part 2: Letters. 38, 12 A

研究成果: Article › 同行評審

Comparison of novel cleaning solutions with various chelating agents for post-CMP cleaning on poly-Si film

Pan, T. M., Lei, T. F., Ko, F-H., Chao, T-S., Chiu, T. H., Lee, Y. H. & Lu, C. P., 1 11月 2001, 於: IEEE Transactions on Semiconductor Manufacturing. 14, 4, p. 365-371 7 p., 964323.

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14 引文斯高帕斯（Scopus）

Comparison of ultrathin CoTiO₃ and NiTiO₃ high-k gate dielectrics

Pan, T. M., Lei, T. F. & Chao, T-S., 15 3月 2001, 於: Journal of Applied Physics. 89, 6, p. 3447-3452 6 p.

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28 引文斯高帕斯（Scopus）

Complementary carbon nanotube-gated carbon nanotube thin-film transistor

Chen, B. H., Lin, H-C., Huang, T. Y., Wei, J. H., Wang, H. H., Tsai, M. J. & Chao, T-S., 27 2月 2006, 於: Applied Physics Letters. 88, 9, 093502.

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19 引文斯高帕斯（Scopus）

Comprehensive Analysis on Electrical Characteristics of Pi-Gate Poly-Si Junctionless FETs

Hsieh, D. R., Lin, J. Y., Kuo, P. Y. & Chao, T-S., 1 7月 2017, 於: IEEE Transactions on Electron Devices. 64, 7, p. 2992-2998 7 p., 7934337.

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10 引文斯高帕斯（Scopus）

Comprehensive study on a novel bidirectional tunneling program/erase NOR-type (BiNOR) 3-D flash memory cell

Chou, A. H. F., Yang, E. C. S., Liu, C. J., Pong, H. H., Liaw, M. C., Chao, T-S., King, Y. C., Hwang, H. L. & Hsu, C. C. H., 1 7月 2001, 於: IEEE Transactions on Electron Devices. 48, 7, p. 1386-1393 8 p.

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3 引文斯高帕斯（Scopus）

CoTiO₃ high-κ dielectrics on HSG for DRAM applications

Chao, T-S., Ku, W. M., Lin, H. C., Landheer, D., Wang, Y. Y. & Mori, Y., 1 12月 2004, 於: IEEE Transactions on Electron Devices. 51, 12, p. 2200-2204 5 p.

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20 引文斯高帕斯（Scopus）

趙 天生

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趙天生