陳 添福

研究成果

每年研究成果 1991 2004 2005 2009 2013 2014 2015 2016 2017 2023

• 46 Conference contribution
• 40 Article
• 7 Conference article
• 2 Chapter
• 4 更多
  • 2 Paper
  • 2 Patent

每年研究成果

每年研究成果

搜尋結果

• 2004

  A parameterized power-aware IP core generator for the 2-D 8×8 DCT/IDCT

  Ju, R. C., Chen, J. W., Guo, J-I. & Chen, T-F., 7 9月 2004, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 2

  研究成果: Conference article › 同行評審

  • Intellectual property core 100%
  • Adders 42%
  • Energy dissipation 33%
  • Costs 29%
  • Electric power utilization 28%
  3 引文 斯高帕斯（Scopus）

• A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms

  Chen, K. H., Guo, J-I., Wang, J. S., Yeh, C. W. & Chen, T-F., 7 9月 2004, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 2

  研究成果: Conference article › 同行評審

  • Intellectual property core 100%
  • Random access storage 57%
  • Adders 28%
  • Textures 20%
  • Costs 19%
  8 引文 斯高帕斯（Scopus）

• A power-aware IP core generator for the one-dimensional discrete fourier transform

  Chien, C. D., Lin, C. C., Guo, J-I. & Chen, T-F., 7 9月 2004, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 3

  研究成果: Conference article › 同行評審

  • Intellectual property core 100%
  • Discrete Fourier transforms 85%
  • Design for testability 43%
  • Computer hardware 27%
  • Cost reduction 15%
  1 引文 斯高帕斯（Scopus）

• Unified bus encoding by stream reconstruction with variable strides

  Chen, T-F., Hsieh, T. M. & Wei, C. L., 7 9月 2004, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 2

  研究成果: Conference article › 同行評審

  • Energy utilization 100%
  • Embedded systems 65%
  • Capacitance 60%
  • Experiments 25%
• 1996

  Efficient trace-sampling simulation techniques for cache performance analysis

  Chen, T-F., 1 1月 1996, 於: Proceedings of the IEEE Annual Simulation Symposium. p. 54-63 10 p.

  研究成果: Conference article › 同行評審

  • Cache 100%
  • Performance Analysis 84%
  • Trace 54%
  • Sampling 47%
  • Simulation 42%
  3 引文 斯高帕斯（Scopus）
• 1995

  Effective programmable prefetch engine for on-chip caches

  Chen, T-F., 1 12月 1995, 於: Proceedings of the Annual International Symposium on Microarchitecture. p. 237-242 6 p.

  研究成果: Conference article › 同行評審

  • Engines 100%
  • Cost effectiveness 55%
  • Data storage equipment 31%
  24 引文 斯高帕斯（Scopus）
• 1994

  Performance study of software and hardware data prefetching schemes

  Chen, T-F. & Baer, J. L., 1 1月 1994, 於: Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA. p. 223-232 10 p.

  研究成果: Conference article › 同行評審

  • Computer hardware 100%
  • Data storage equipment 69%
  111 引文 斯高帕斯（Scopus）