Shyh-Jye Jerry Jou

2022

A 14 μJ/Decision Keyword Spotting Accelerator With In-SRAM-Computing and On Chip Learning for Customization

Chiang, Y. H., Chang, T-S. & Jou, S. J., 2022, (Accepted/In press) 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-9 9 p.

研究成果: Article › 同行評審

A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers

Jen, C-W., Liu, H. C., Huang, Z. C., Xue, N. C. & Jou, S. J. J., 2022, (Accepted/In press) 於: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. p. 1 1 p.

研究成果: Article › 同行評審

Hardware-Robust In-RRAM-Computing for Object Detection

Chiang, Y. H., Ni, C. E., Sung, Y., Hou, T. H., Chang, T. S. & Jou, S. J., 2022, (Accepted/In press) 於: IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications

Davila, H. L., Wu, T. H., Jou, S. J. J., Chen, S. G. & Tsai, P. Y., 2022, (Accepted/In press) 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-0 2 p.

研究成果: Article › 同行評審

2021

A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems

Chan, H. W., Lee, W. C., Chiu, K. L., Jen, C-W. & Jou, S-J., 5月 2021, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 29, 5, p. 904 - 915 12 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System

Liu, H. C., Huang, Z. C., Doan, N. G., Jen, C-W. & Jou, S-J., 10月 2021, (E-pub ahead of print) 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 14 p.

研究成果: Article › 同行評審

2020

A 75-Gb/s/mm² and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm

Lopez, H., Chan, H. W., Chiu, K. L., Tsai, P. Y. & Jou, S. J. J., 4月 2020, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28, 4, p. 926-939 14 p., 8935206.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

Design of Downlink Synchronization for Millimeter Wave Cellular System Based on Multipath Division Multiple Access

Chiu, K. L., Shen, P. H., Lin, B. R., Hsiao, W. H., Jou, S-J. J. & Huang, C-C., 1 1月 2020, (Accepted/In press) 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 67, 9, p. 3211 - 3223 13 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

2017

A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band

Liu, C. Y., Leong, E. W. J., Wu, C. T., Sie, M. S., Lopez, H., Jen, C-W. & Jou, S-J., 1 12月 2017, 於: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 7, 4, p. 558-568 11 p., 8025344.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

Dual-Mode All-Digital Baseband Receiver with a Feed-Forward and Shared-Memory Architecture for Dual-Standard over 60 GHz NLOS Channel

Liu, C. Y., Sie, M. S., Leong, E. W. J., Yao, Y. C., Jen, C-W., Liu, W. C., Wu, C. F. & Jou, S-J., 1 3月 2017, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 3, p. 608-618 11 p., 7795161.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

2016

An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver

Liu, C. Y., Sie, M. S., Leong, E. W. J., Yao, Y. C., Lopez, H., Jen, C. W., Liu, W. C. & Jou, S. J., 1 12月 2016, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 63, 12, p. 2347-2356 10 p., 7748506.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

A systematic ANSI S1.11 filter bank specification relaxation and its efficient multirate architecture for hearing-aid systems

Yang, C. Y., Liu, C-W. & Jou, S-J., 1 8月 2016, 於: IEEE/ACM Transactions on Audio Speech and Language Processing. 24, 8, p. 1380-1392 13 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

A varactor-based all-digital multi-phase PLL with random-sampling spur suppression techniques

Chang, C. W., Lo, K. Y., Ibrahim, H. A., Su, M. C., Chu, Y. H. & Jou, S-J., 1 4月 2016, 於: IEICE Transactions on Electronics. E99C, 4, p. 481-490 10 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series

He, W. Q., Chen, Y. H. & Jou, S-J., 1 8月 2016, 於: Circuits, Systems, and Signal Processing. 35, 8, p. 2972-2991 20 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver

Wu, C. F., Liu, W. C., Tsui, C. C., Liu, C. Y., Sie, M. S. & Jou, S-J., 1 11月 2016, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 11, p. 3323-3333 11 p., 7460982.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Near-threshold all-digital PLL with dynamic voltage scaling power management

Chang, C. W., Chang, K. Y., Chu, Y. H. & Jou, S-J., 21 1月 2016, 於: Electronics Letters. 52, 2, p. 109-111 3 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

2015

A 0.325 V, 600-kHz, 40-nm 72-kb 9T subthreshold SRAM with aligned boosted write wordline and negative write bitline write-assist

Lu, C. Y., Chuang, C. T., Jou, S-J., Tu, M. H., Wu, Y. P., Huang, C. P., Kan, P. S., Huang, H. S., Lee, K. D. & Kao, Y. S., 1 5月 2015, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 5, p. 958-962 5 p., 6812218.

研究成果: Article › 同行評審

30 引文斯高帕斯（Scopus）

A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression

Su, M. C., Chen, W-Z., Wu, P. S., Chen, Y. H., Lee, C. C. & Jou, S-J., 1 3月 2015, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 62, 3, p. 743-751 9 p., 06977996.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

All-digital synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad

Liu, W. C., Wei, T. C., Huang, Y. S., Chan, C. D. & Jou, S-J., 1 2月 2015, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 62, 2, p. 545-553 9 p., 6932507.

研究成果: Article › 同行評審

46 引文斯高帕斯（Scopus）

A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs

Su, M. C., Jou, S-J. & Chen, W-Z., 1 4月 2015, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23, 4, p. 766-770 5 p., 6798731.

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

A near-threshold cell-based all-digital PLL with hierarchical band-selection G-DCO for fast lock-in and low-power applications

Chang, C. W., Chu, Y. H. & Jou, S-J., 1 8月 2015, 於: IEICE Transactions on Electronics. E98C, 8, p. 882-891 10 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

He, W. Q., Chen, Y. H. & Jou, S-J., 1 8月 2015, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 62, 8, p. 2052-2061 10 p., 7166389.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

2014

40 nm bit-interleaving 12t subthreshold sram with data-aware write-assist

Chiu, Y. W., Hu, Y. H., Tu, M. H., Zhao, J. K., Chu, Y. H., Jou, S-J. & Chuang, C. T., 1 1月 2014, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 9, p. 2578-2585 8 p., 6883245.

研究成果: Article › 同行評審

115 引文斯高帕斯（Scopus）

A 40 nm 512 kb cross-point 8 T pipeline SRAM with binary word-line boosting control, ripple bit-line and adaptive data-aware write-assist

Lien, N. C., Chu, L. W., Chen, C. H., Yang, H. I., Tu, M. H., Kan, P. S., Hu, Y. J., Chuang, C. T., Jou, S-J. & Hwang, W., 1 1月 2014, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 12, p. 3416-3425 10 p., 6891326.

研究成果: Article › 同行評審

32 引文斯高帕斯（Scopus）

Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application

Wei, C. W., Tsai, C. C., Fan Jiang, Y., Chang, T-S. & Jou, S-J., 1 11月 2014, 於: IET Circuits, Devices and Systems. 8, 6, p. 516-525 10 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Blind ICA detection based on second-order cone programming for MC-CDMA systems

Jen, C. W. & Jou, S. J., 1 12月 2014, 於: Eurasip Journal on Advances in Signal Processing. 2014, 1, p. 1-14 14 p.

研究成果: Article › 同行評審

開啟存取

7 引文斯高帕斯（Scopus）

Continuous-flow parallel bit-reversal circuit for MDF and MDC FFT architectures

Chen, S-G., Huang, S. J., Garrido, M. & Jou, S-J., 1 10月 2014, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 10, p. 2869-2877 9 p., 6849501.

研究成果: Article › 同行評審

27 引文斯高帕斯（Scopus）

Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing

FanChiang, Y., Wei, C. W., Meng, Y. L., Lin, Y. W., Jou, S-J. & Chang, T-S., 1 8月 2014, 於: IEEE Transactions on Audio, Speech and Language Processing. 22, 8, p. 1248-1259 12 p., 2327300.

研究成果: Article › 同行評審

20 引文斯高帕斯（Scopus）

Neuromorphic pitch based noise reduction for monosyllable hearing aid system application

Chen, Y. J., Wei, C. W., Fanchiang, Y., Meng, Y. L., Huang, Y. C. & Jou, S-J., 1 2月 2014, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 2, p. 463-475 13 p., 6716078.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

2013

A digital golay-MPIC time domain equalizer for SC/OFDM dual-modes at 60 GHz band

Liu, W. C., Yeh, F. C., Wei, T. C., Chan, C. D. & Jou, S-J., 26 3月 2013, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 60, 10, p. 2730-2739 10 p., 6484199.

研究成果: Article › 同行評審

20 引文斯高帕斯（Scopus）

A low-overhead interference canceller for high-mobility STBC-OFDM systems

Chen, H. Y., Chang, W. K. & Jou, S-J., 26 3月 2013, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 60, 10, p. 2763-2773 11 p., 6481474.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

A low-power level-converting double-edge-triggered flip-flop design

Wang, L. R., Lo, K. Y. & Jou, S-J., 1 1月 2013, 於: IEICE Transactions on Electronics. E96-C, 10, p. 1351-1355 5 p.

研究成果: Article › 同行評審

STBC-OFDM downlink baseband receiver for mobile WMAN

Chen, H. Y., Lin, J. N., Hu, H. S. & Jou, S-J., 1 1月 2013, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 1, p. 43-54 12 p., 6138894.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

2012

A 0.33-V, 500-kHz, 3.94-μW 40-nm 72-Kb 9T subthreshold SRAM with ripple bit-line structure and negative bit-line write-assist

Lu, C. Y., Tu, M. H., Yang, H. I., Wu, Y. P., Huang, H. S., Lin, Y. J., Lee, K. D., Kao, Y. S., Chuang, C. T., Jou, S-J. & Hwang, W., 1 12月 2012, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 59, 12, p. 863-867 5 p., 6423268.

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

A 5.79-Gb/s energy-efficient multirate LDPC codec chip for IEEE 802.15.3c applications

Yen, S. W., Hung, S. Y., Chen, C. L., Chang, H-C., Jou, S-J. & Lee, C-Y., 15 5月 2012, 於: IEEE Journal of Solid-State Circuits. 47, 9, p. 2246-2257 12 p., 6198294.

研究成果: Article › 同行評審

49 引文斯高帕斯（Scopus）

A single-ended disturb-free 9T subthreshold SRAM with cross-point data-aware write word-line structure, negative bit-line, and adaptive read operation timing tracing

Tu, M. H., Lin, J. Y., Tsai, M. C., Lu, C. Y., Lin, Y. J., Wang, M. H., Huang, H. S., Lee, K. D., Shih, W. C., Jou, S-J. & Chuang, C. T., 18 4月 2012, 於: IEEE Journal of Solid-State Circuits. 47, 6, p. 1469-1482 14 p., 6183492.

研究成果: Article › 同行評審

140 引文斯高帕斯（Scopus）

High throughput concurrent lookahead adaptive decision feedback equaliser

Lin, Y. C., Jou, S-J. & Shiue, M. T., 1 1月 2012, 於: IET Circuits, Devices and Systems. 6, 1, p. 52-62 11 p.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

High throughput extended incremental coefficient-lookahead filters based adaptive decision feedback equalizer

Lin, Y. C., Shiue, M. T. & Jou, S-J., 1 6月 2012, 於: International Journal of Electrical Engineering. 19, 3, p. 115-126 12 p.

研究成果: Article › 同行評審

Sub μW noise reduction for CIC hearing aids

Wei, C. W., Su, S. J., Chang, T-S. & Jou, S-J., 1 5月 2012, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 5, p. 937-947 11 p., 5740627.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

2011

Well-structured modified booth multiplier and its application to reconfigurable MAC design

Wang, L. R., Tu, M. H., Jou, S-J. & Lee, C. L., 1 1月 2011, 於: IEICE Transactions on Electronics. E94-C, 6, p. 1112-1119 8 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

2010

A robust channel estimator for high-mobility STBC-OFDM systems

Chen, H. Y., Ku, M. L., Jou, S-J. & Huang, C-C., 1 1月 2010, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 57, 4, p. 925-936 12 p., 5357412.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

Single-ended subthreshold SRAM with asymmetrical write/read-assist

Tu, M. H., Lin, J. Y., Tsai, M. C., Jou, S-J. & Chuang, C. T., 15 11月 2010, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 57, 12, p. 3039-3047 9 p., 5634142.

研究成果: Article › 同行評審

105 引文斯高帕斯（Scopus）

2009

Design of a multimode QC-LDPC decoder based on shift-routing network

Liu, C. H., Lin, C. C., Yen, S. W., Chen, C. L., Chang, H-C., Lee, C-Y., Hsu, Y. S. & Jou, S-J., 11 9月 2009, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 56, 9, p. 734-738 5 p.

研究成果: Article › 同行評審

29 引文斯高帕斯（Scopus）

Low complexity synchronization design of an OFDM receiver for DVB-T/H

Wei, T. C., Liu, W. C., Tseng, C. Y. & Jou, S-J., 25 8月 2009, 於: IEEE Transactions on Consumer Electronics. 55, 2, p. 408-413 6 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

2008

A jointed mode detection and symbol detection scheme for DVB-T

Wei, T. C., Liu, W. C. & Jou, S-J., 1 5月 2008, 於: IEEE Transactions on Consumer Electronics. 54, 2, p. 336-341 6 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

An LDPC decoder chip based on self-routing network for IEEE 802.16e applications

Liu, C. H., Yen, S. W., Chen, C. L., Chang, H-C., Lee, C-Y., Hsu, Y. S. & Jou, S-J., 1 3月 2008, 於: IEEE Journal of Solid-State Circuits. 43, 3, p. 684-694 11 p., 4456784.

研究成果: Article › 同行評審

107 引文斯高帕斯（Scopus）

Introduction to the special section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)

Lu, N. & Jou, S-J., 1 11月 2008, 於: IEEE Journal of Solid-State Circuits. 43, 11, p. 2352-2353 2 p., 4685430.

研究成果: Article › 同行評審

2007

Design and analysis of digital data recovery circuits using oversampling

Jou, S-J., Lin, C. H., Chen, Y. H. & Li, Z. H., 19 4月 2007, 於: IET Circuits, Devices and Systems. 1, 1, p. 93-101 9 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

2006

Bit-error-rate analysis for clock and data recovery based on blind oversampling technique

Jou, S-J., Lin, C. H. & Wang, Y. I., 1 8月 2006, 於: International Journal of Electrical Engineering. 13, 3, p. 219-228 10 p.

研究成果: Article › 同行評審

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling

Chen, H. Y. & Jou, S-J., 1 1月 2006, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 53, 9, p. 827-831 5 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

周 世傑

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周世傑