Shyh-Jye Jerry Jou

Article

Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series

He, W. Q., Chen, Y. H. & Jou, S-J., 1 8月 2016, 於: Circuits, Systems, and Signal Processing. 35, 8, p. 2972-2991 20 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

EMOTA. An event-driven MOS timing simulator for VLSI circuits

Shen, W. Z., Jou, S-J. & Tao, Y. S., 1 8月 1990, 於: IEE proceedings. Part G. Electronic circuits and systems. 137, 4, p. 279-290 12 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Event-driven incremental timing fault simulator

Jou, S-J., Chiou, S. H., Tao, Y. S. & Shen, W. Z., 1 1月 1993, 於: IEE Proceedings, Part G: Circuits, Devices and Systems. 140, 1, p. 45-54 10 p.

研究成果: Article › 同行評審

Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver

Wu, C. F., Liu, W. C., Tsui, C. C., Liu, C. Y., Sie, M. S. & Jou, S-J., 1 11月 2016, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24, 11, p. 3323-3333 11 p., 7460982.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Hardware nested loop with buffer of parameterized and embedded DSP core

Tsao, Y. L., Chen, W. H. & Jou, S-J., 11月 2005, 於: International Journal of Electrical Engineering. 12, 4, p. 357-364 8 p.

研究成果: Article › 同行評審

Hardware-Robust In-RRAM-Computing for Object Detection

Chiang, Y. H., Ni, C. E., Sung, Y., Hou, T. H., Chang, T. S. & Jou, S. J., 2022, (Accepted/In press) 於: IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Hierarchical techniques for symbolic analysis of electronic circuits

Jou, S-J., Perng, M. F. & Su, C-C., 1 1月 1997, 於: IEE Proceedings: Circuits, Devices and Systems. 144, 3, p. 167-177 11 p.

研究成果: Article › 同行評審

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

He, W. Q., Chen, Y. H. & Jou, S-J., 1 8月 2015, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 62, 8, p. 2052-2061 10 p., 7166389.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

High throughput concurrent lookahead adaptive decision feedback equaliser

Lin, Y. C., Jou, S-J. & Shiue, M. T., 1 1月 2012, 於: IET Circuits, Devices and Systems. 6, 1, p. 52-62 11 p.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

High throughput extended incremental coefficient-lookahead filters based adaptive decision feedback equalizer

Lin, Y. C., Shiue, M. T. & Jou, S-J., 1 6月 2012, 於: International Journal of Electrical Engineering. 19, 3, p. 115-126 12 p.

研究成果: Article › 同行評審

Intrinsic response for analog module testing using an analog testability bus

Su, C-C., Chen, Y. T. & Jou, S-J., 1 1月 2001, 於: ACM Transactions on Design Automation of Electronic Systems. 6, 2, p. 226-243 18 p.

研究成果: Article › 同行評審

Introduction to the special section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)

Lu, N. & Jou, S-J., 1 11月 2008, 於: IEEE Journal of Solid-State Circuits. 43, 11, p. 2352-2353 2 p., 4685430.

研究成果: Article › 同行評審

Joint Digital Online Compensation of TX and RX Time-Varying I/Q Mismatch and DC-Offset in mmWave Transceiver System

Liu, H. C., Huang, Z. C., Doan, N. G., Jen, C-W. & Jou, S-J., 10月 2021, (E-pub ahead of print) 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 14 p.

研究成果: Article › 同行評審

Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing

FanChiang, Y., Wei, C. W., Meng, Y. L., Lin, Y. W., Jou, S-J. & Chang, T-S., 1 8月 2014, 於: IEEE Transactions on Audio, Speech and Language Processing. 22, 8, p. 1248-1259 12 p., 2327300.

研究成果: Article › 同行評審

20 引文斯高帕斯（Scopus）

Low complexity synchronization design of an OFDM receiver for DVB-T/H

Wei, T. C., Liu, W. C., Tseng, C. Y. & Jou, S-J., 25 8月 2009, 於: IEEE Transactions on Consumer Electronics. 55, 2, p. 408-413 6 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Low-Error Reduced-Width Booth Multipliers for DSP Applications

Jou, S-J., Tsai, M. H. & Tsao, Y. L., 1 11月 2003, 於: IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications. 50, 11, p. 1470-1474 5 p.

研究成果: Article › 同行評審

57 引文斯高帕斯（Scopus）

Low-power embedded DSP core for communication systems

Tsao, Y. L., Chen, W. H., Tan, M. H., Lin, M. C. & Jou, S-J., 1 12月 2003, 於: Eurasip Journal on Applied Signal Processing. 2003, 13, p. 1355-1370 16 p.

研究成果: Article › 同行評審

開啟存取

7 引文斯高帕斯（Scopus）

Low-power multirate architecture for if digital frequency down converter

Jou, S-J., Wu, S. Y. & Wang, C. K., 1 12月 1998, 於: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 11, p. 1487-1494 8 p.

研究成果: Article › 同行評審

18 引文斯高帕斯（Scopus）

Low-power self-timed circuit design technique

Jou, S-J. & Chung, I. Y., 16 1月 1997, 於: Electronics Letters. 33, 2, p. 110-111 2 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Low Routing Complexity Multiframe Pipelined LDPC Decoder Based on a Novel Pseudo Marginalized Min-Sum Algorithm for High Throughput Applications

Davila, H. L., Wu, T. H., Jou, S. J. J., Chen, S. G. & Tsai, P. Y., 2022, (Accepted/In press) 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-0 2 p.

研究成果: Article › 同行評審

Low switching noise and load-adaptive output buffer design techniques

Jou, S-J., Kuo, S. H., Chiu, J. T. & Lin, T. H., 1 8月 2001, 於: IEEE Journal of Solid-State Circuits. 36, 8, p. 1239-1249 11 p.

研究成果: Article › 同行評審

31 引文斯高帕斯（Scopus）

MOTA: A MOSFET TIMING SIMULATOR.

Jou, S-J., Jen, C. W., Shen, W. Z. & Lee, C. L., 1 1月 1986, 於: IEE Proceedings I: Solid State and Electron Devices. 133, 5, p. 193-199 7 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Multi-gigabit pre-emphasis design and analysis for serial link

Lin, C. H., Tsai, C. H., Chen, C. N. & Jou, S-J., 1 1月 2005, 於: IEICE Transactions on Electronics. E88-C, 10, p. 2009-2019 11 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Multiplierless FIR filter architecture synthesizer based on CSD code

Lin, M. C., Chen, C. L., Hsin, D. Y., Lin, C. H. & Jou, S-J., 1 5月 2003, 於: Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an. 10, 2, p. 155-163 9 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Near-threshold all-digital PLL with dynamic voltage scaling power management

Chang, C. W., Chang, K. Y., Chu, Y. H. & Jou, S-J., 21 1月 2016, 於: Electronics Letters. 52, 2, p. 109-111 3 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Neuromorphic pitch based noise reduction for monosyllable hearing aid system application

Chen, Y. J., Wei, C. W., Fanchiang, Y., Meng, Y. L., Huang, Y. C. & Jou, S-J., 1 2月 2014, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 61, 2, p. 463-475 13 p., 6716078.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

On-chip voltage down converter for low-power digital system

Jou, S-J. & Chen, T. L., 1 12月 1998, 於: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 45, 5, p. 617-625 9 p.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

Parallel event-driven MOS timing simulator on distributed memory multiprocessors

Hsieh, W. H., Jou, S-J. & Su, C-C., 8月 1996, 於: IEE Proceedings: Circuits, Devices and Systems. 143, 4, p. 207-212 6 p.

研究成果: Article › 同行評審

Parallel Scrambler for High-Speed Applications

Lin, C. H., Chen, C. N., Wang, Y. J., Hsiac, J. Y. & Jou, S-J., 6 7月 2006, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 53, 7, p. 558-562 5 p.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

Simulatable timing model for MOS logic circuit

Jou, S-J., Shen, W. Z., Jen, C. W. & Lee, C. L., 1 1月 1987, 於: IEE Proceedings G: Electronics Circuits and Systems. 134, 6, p. 276-284 9 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Simultaneous switching noise analysis and low-bounce buffer design

Jou, S-J., Cheng, W. C. & Lin, Y. T., 1 12月 2001, 於: IEE Proceedings: Circuits, Devices and Systems. 148, 6, p. 303-311 9 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

Single-ended subthreshold SRAM with asymmetrical write/read-assist

Tu, M. H., Lin, J. Y., Tsai, M. C., Jou, S-J. & Chuang, C. T., 15 11月 2010, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 57, 12, p. 3039-3047 9 p., 5634142.

研究成果: Article › 同行評審

105 引文斯高帕斯（Scopus）

STBC-OFDM downlink baseband receiver for mobile WMAN

Chen, H. Y., Lin, J. N., Hu, H. S. & Jou, S-J., 1 1月 2013, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 21, 1, p. 43-54 12 p., 6138894.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

Sub μW noise reduction for CIC hearing aids

Wei, C. W., Su, S. J., Chang, T-S. & Jou, S-J., 1 5月 2012, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20, 5, p. 937-947 11 p., 5740627.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Well-structured modified booth multiplier and its application to reconfigurable MAC design

Wang, L. R., Tu, M. H., Jou, S-J. & Lee, C. L., 1 1月 2011, 於: IEICE Transactions on Electronics. E94-C, 6, p. 1112-1119 8 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

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