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查看斯高帕斯 (Scopus) 概要
周 世傑
教授
電機資訊國際博士學位學程
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1850
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21
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按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
335
引文
9
h-指數
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83
引文
5
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1900 …
2024
每年研究成果
概覽
指紋
網路
計畫
(38)
研究成果
(241)
獎項
(2)
類似的個人檔案
(6)
指紋
查看啟用 Shyh-Jye Jerry Jou 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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重量
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Keyphrases
60 GHz Band
24%
64QAM
18%
6T-SRAM
27%
Adaptive Decision Feedback Equalizer
27%
All-digital
49%
Baseband Receiver
46%
Bitline
31%
Channel Estimation
24%
Clock Recovery
19%
CMOS Process
47%
CMOS Technology
32%
Communication Systems
23%
Data-aware
33%
Decoder
19%
Design Techniques
24%
Digital Video Broadcasting-terrestrial (DVB-T)
27%
Digitally Controlled Oscillator
21%
DSP Core
23%
Dual-mode
40%
Filter Bank
18%
FIR Filter
16%
Frequency Domain Equalizer
18%
Gate Count
25%
Gbps
30%
Hardware Complexity
24%
Hearing Aids
39%
High-throughput
22%
IEEE 802.15.3c
34%
Low Jitter
18%
Low Power
83%
Measurement Results
23%
Millimeter Wave
29%
Multi-rate
24%
Noise Reduction
18%
On chip
25%
Operation Frequency
18%
Orthogonal Frequency Division multiplexing
21%
Parallelization
35%
Power Consumption
59%
Proposed Design
21%
Pulse Amplitude Modulation
18%
Reconfigurable
21%
Serial Link Transmitter
28%
Single-carrier
32%
Static Random Access Memory
16%
Subthreshold SRAM
28%
Throughput Rate
23%
Transmitter
23%
Wordline
29%
Write Assist
43%
Engineering
Bit Error Rate
27%
Bit Line
31%
Carrier Frequency
26%
Channel Estimation
34%
Clock Rate
14%
Communication System
23%
Computational Complexity
16%
Correlator
12%
Critical Path
13%
Cross Point
20%
Data Rate
15%
Decision Feedback Equalizers
32%
Design Result
21%
Design Technique
23%
Digital Baseband
27%
Domain Equalizer
29%
Electric Power Utilization
100%
Energy Conservation
15%
Energy Efficiency
15%
Equalizers
33%
Feedforward
22%
Filter Banks
28%
Finite Impulse Response Filter
16%
Frequency Domain
28%
Frequency Operation
27%
Hardware Complexity
36%
Input Data
16%
Interconnects
15%
Millimeter Wave
26%
Multistage
13%
Network Routing
16%
Noise Cancellation
14%
Operating Frequency
25%
Orthogonal Frequency Division Multiplexing
27%
Oscillator
30%
Parallelism
40%
Performance Standard
18%
Phase Locked Loop
34%
Phase Noise
15%
Power Supply
14%
Pulse Amplitude Modulation
17%
Quadrature Amplitude Modulation
16%
Quadrature Phase Shift Keying
13%
Random Access Memory
16%
Simulation Result
45%
Speed Operation
27%
Supply Voltage
14%
Time Domain
18%
Transceiver
56%
Voltage Scaling
13%
Computer Science
Analog-to-Digital Converter
7%
Application Specific Integrated Circuit
9%
Approximation (Algorithm)
11%
Architecture Design
10%
carrier frequency offset
17%
channel estimate
10%
Channel Estimation
26%
Computational Complexity
11%
Computer Hardware
64%
Critical Path
8%
Critical Path Delay
7%
Data Recovery
13%
Design Parameter
8%
Digital Frequency
11%
Distributed Memory (Multiprocessor)
7%
Energy Efficiency
18%
Energy Efficient
8%
Execution Time
7%
Filter Bank
20%
Finite Impulse Response Filter
18%
Frequency Domain
15%
Hardware Implementation
20%
Hardware Overhead
8%
High Throughput
19%
Memory Access
13%
min-sum algorithm
13%
multi carrier
11%
Network Routing
15%
Noise Margin
7%
Noise Suppression
9%
Operating Frequency
8%
Orthogonal Frequency Division Multiplexing
16%
Parallel Simulation
10%
Parallelism
46%
Power Amplifier
9%
Power Consumption
76%
Pulse Amplitude Modulation
11%
Quadrature Phase Shift Keying
9%
Read Operation
12%
Reduce Power Consumption
11%
Simulation Mode
13%
single carrier
32%
space time block code
7%
Spectral Subtraction
11%
Static Random Access Memory
8%
Supply Voltage
11%
Threshold Voltage
19%
Verilog
8%
Voice Activity Detection
14%
Wireless Communication
11%
