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查看斯高帕斯 (Scopus) 概要
周 世傑
教授
電機資訊國際博士學位學程
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1840
引文
20
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
583
引文
11
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
84
引文
5
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1900 …
2024
每年研究成果
概覽
指紋
網路
計畫
(38)
研究成果
(240)
獎項
(2)
類似的個人檔案
(6)
指紋
查看啟用 Shyh-Jye Jerry Jou 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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重量
按字母排序
Keyphrases
Low Power
83%
Power Consumption
59%
All-digital
49%
CMOS Process
47%
Baseband Receiver
46%
Write Assist
43%
Dual-mode
40%
Hearing Aids
39%
Parallelization
35%
IEEE 802.15.3c
34%
Data-aware
33%
CMOS Technology
32%
Single-carrier
32%
Bitline
31%
Gbps
30%
Wordline
29%
Millimeter Wave
29%
Serial Link Transmitter
28%
Subthreshold SRAM
28%
6T-SRAM
27%
Adaptive Decision Feedback Equalizer
27%
Digital Video Broadcasting-terrestrial (DVB-T)
27%
On chip
25%
Gate Count
25%
Multi-rate
24%
Hardware Complexity
24%
60 GHz Band
24%
Design Techniques
24%
Channel Estimation
24%
Communication Systems
23%
Transmitter
23%
Measurement Results
23%
DSP Core
23%
Throughput Rate
23%
High-throughput
22%
Digitally Controlled Oscillator
21%
Reconfigurable
21%
Orthogonal Frequency Division multiplexing
21%
Proposed Design
21%
Clock Recovery
19%
Decoder
19%
Operation Frequency
18%
Frequency Domain Equalizer
18%
Low Jitter
18%
Noise Reduction
18%
64QAM
18%
Filter Bank
18%
Pulse Amplitude Modulation
18%
Static Random Access Memory
16%
FIR Filter
16%
Engineering
Electric Power Utilization
100%
Transceiver
56%
Simulation Result
45%
Parallelism
40%
Hardware Complexity
34%
Phase Locked Loop
34%
Equalizers
33%
Decision Feedback Equalizers
32%
Bit Line
31%
Channel Estimation
30%
Oscillator
30%
Domain Equalizer
29%
Filter Banks
28%
Frequency Domain
28%
Orthogonal Frequency Division Multiplexing
27%
Speed Operation
27%
Digital Baseband
27%
Frequency Operation
27%
Millimeter Wave
26%
Carrier Frequency
26%
Operating Frequency
25%
Bit Error Rate
25%
Design Technique
23%
Communication System
23%
Feedforward
22%
Design Result
21%
Cross Point
20%
Time Domain
18%
Performance Standard
18%
Pulse Amplitude Modulation
17%
Computational Complexity
16%
Input Data
16%
Finite Impulse Response Filter
16%
Network Routing
16%
Random Access Memory
16%
Interconnects
15%
Energy Efficiency
15%
Energy Conservation
15%
Data Rate
15%
Phase Noise
15%
Quadrature Amplitude Modulation
14%
Supply Voltage
14%
Power Supply
14%
Noise Cancellation
14%
Critical Path
13%
Quadrature Phase Shift Keying
13%
Voltage Scaling
13%
Multistage
13%
Clock Rate
13%
Signal-to-Noise Ratio
12%
Computer Science
Power Consumption
76%
Computer Hardware
60%
Parallelism
46%
single carrier
32%
Channel Estimation
23%
Filter Bank
20%
Hardware Implementation
20%
Threshold Voltage
19%
High Throughput
19%
Energy Efficiency
18%
Finite Impulse Response Filter
18%
carrier frequency offset
17%
Orthogonal Frequency Division Multiplexing
16%
Network Routing
15%
Frequency Domain
15%
Voice Activity Detection
14%
Data Recovery
13%
Simulation Mode
13%
min-sum algorithm
13%
Memory Access
13%
Read Operation
12%
Computational Complexity
11%
Spectral Subtraction
11%
Reduce Power Consumption
11%
Wireless Communication
11%
multi carrier
11%
Supply Voltage
11%
Approximation (Algorithm)
11%
Digital Frequency
11%
Pulse Amplitude Modulation
11%
Parallel Simulation
10%
channel estimate
10%
Architecture Design
10%
Application Specific Integrated Circuit
9%
Noise Suppression
9%
Power Amplifier
9%
Quadrature Phase Shift Keying
9%
Design Parameter
8%
Operating Frequency
8%
Critical Path
8%
Static Random Access Memory
8%
Verilog
8%
Energy Efficient
8%
Hardware Overhead
8%
Distributed Memory (Multiprocessor)
7%
Noise Margin
7%
Execution Time
7%
space time block code
7%
Analog-to-Digital Converter
7%
Critical Path Delay
7%
