每年專案
個人檔案
經歷
2004/08-迄今 國立交通大學電子工程學系/電子研究所教授
2011/04-2014/03 教育部智慧電子國家型科技計畫—智慧電子整合性人才培育辦公室(總聯盟)召集人
2011/08-2015/12 國立交通大學國際長
2016/01-2017/12 科技部科教發展及國際合作司司長
教育/學術資格
PhD, 電子工程, National Chiao Tung University
外部位置
Ministry of Science and Technology
1 1月 2016 → 31 12月 2017
National Central University, Chung-Li, Taiwan
1 8月 1990 → 31 7月 2004
指紋
查看啟用 Shyh-Jye Jerry Jou 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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網路
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料,或
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6G低軌道衛星通訊系統關鍵技術與模組開發-總計畫暨子計畫二:6G衛星通訊系統時變通道及傳送與接收硬體模組之自適應補償器演算法開發與基頻處理器設計
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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創新性新世代5G行動通訊毫米波蜂巢式系統架構與關鍵模組設計-總計畫暨子計畫四:基於新波形與全雙工技術之新世代5G行動通訊毫米波無線基頻傳收機設計
1/08/17 → …
研究計畫: Other Government Ministry Institute
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創新性新世代5G行動通訊毫米波蜂巢式系統架構與關鍵模組設計-總計畫暨子計畫四:基於新波形與全雙工技術之新世代5G行動通訊毫米波無線基頻傳收機設計
1/08/16 → …
研究計畫: Other Government Ministry Institute
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On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC
Chiang, C. Y., Hu, C. L., Lin, M. P. H., Chung, Y. S., Jou, S. J., Wu, J-T., Chiang, S. H. W., Liu, C-N. & Chen, H-M., 16 1月 2023, ASP-DAC 2023 - 28th Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 352-357 6 p. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).研究成果: Conference contribution › 同行評審
開啟存取 -
A 14 μJ/Decision Keyword Spotting Accelerator With In-SRAM-Computing and On Chip Learning for Customization
Chiang, Y. H., Chang, T-S. & Jou, S. J., 2022, (Accepted/In press) 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. p. 1-9 9 p.研究成果: Article › 同行評審
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A Digital Frequency-Dependent I/Q Imbalance and Group Delay Estimation and Compensation Modules for mmWave Single Carrier Baseband Transceivers
Jen, C-W., Liu, H. C., Huang, Z. C., Xue, N. C. & Jou, S. J. J., 2022, (Accepted/In press) 於: IEEE Journal on Emerging and Selected Topics in Circuits and Systems. p. 1 1 p.研究成果: Article › 同行評審
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An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications
Liu, C., Li, S. T., Pan, T. L., Ni, C. E., Sung, Y., Hu, C. L., Chang, K. Y., Hou, T. H., Chang, T. S. & Jou, S. J., 2022, 2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2022 - Proceedings).研究成果: Conference contribution › 同行評審
1 引文 斯高帕斯(Scopus) -
Compressive Sensing Based Hardware Design for Channel Estimation of Wideband Millimeter Wave Hybrid MIMO System
Tu, C. L., Lin, T. Y., Chiu, K. L., Jou, S. J. & Tsai, P. Y., 2022, IEEE International Symposium on Circuits and Systems, ISCAS 2022. Institute of Electrical and Electronics Engineers Inc., p. 2496-2500 5 p. (Proceedings - IEEE International Symposium on Circuits and Systems; 卷 2022-May).研究成果: Conference contribution › 同行評審