跳至主導覽
跳至搜尋
跳過主要內容
國立陽明交通大學研發優勢分析平台 首頁
English
中文
首頁
人員
單位
研究成果
計畫
獎項
活動
貴重儀器
影響
按專業知識、姓名或所屬機構搜尋
查看斯高帕斯 (Scopus) 概要
黃 柏蒼
副教授
國際半導體產業學院
智慧半導體奈米系統技術研究中心
https://orcid.org/0000-0001-8679-2755
h-index
h10-index
h5-index
715
引文
14
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
431
引文
12
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
165
引文
8
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2004
2025
每年研究成果
概覽
指紋
網路
計畫
(8)
研究成果
(121)
類似的個人檔案
(6)
指紋
查看啟用 Po-Tsang Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Neural Sensing
92%
Through Silicon via
84%
Energy Efficient
84%
Microsystems
69%
Fin Field-effect Transistor (FinFET)
64%
Low Power
55%
Sensing Applications
48%
3D IC
44%
Monolithic 3-D (M3-D)
38%
Ternary Content Addressable Memory
37%
3D Integration
32%
In-memory
31%
Energy Efficiency
30%
Network on chip
28%
Power Consumption
27%
Single Crystal
26%
Interposer
25%
Microprobe Array
24%
First-in-first-out
24%
Subthreshold
24%
Coding Scheme
24%
Back-end-of-line
24%
Convolutional Neural Network
24%
High Density
24%
Ultra-low Power
24%
Probe Array
21%
Power Gating
21%
Deep Neural Network
21%
Wireless
20%
Voltage Regulator
20%
All-digital
20%
Ferroelectric Field-effect Transistor (FeFET)
19%
Packaging Technology
19%
Bitline
19%
CMOS Technology
19%
Two-level
18%
Energy-efficient Accelerator
18%
Accelerator Design
18%
Tri-band
18%
Monolithic 3D IC
18%
Multi-die
18%
Active Bridge
18%
Bridge chip
18%
Circuitry
18%
Resource Utilization
17%
Transceiver
17%
Neural Probe
16%
Silica
16%
On chip
16%
Double-sided
16%
Engineering
Microsystem
75%
Electric Power Utilization
53%
Sensing Application
49%
Interposer
40%
Interlayer
36%
Simulation Result
34%
Energy Conservation
33%
Three Dimensional Integrated Circuits
33%
Energy Efficiency
30%
Line Search
28%
Interconnects
27%
Match Line
26%
Voltage Regulator
24%
Millimeter Wave
24%
Silicon Dioxide
24%
Metrics
23%
Power-Gating Technique
23%
Radio Frequency
22%
Power Control
21%
Transceiver
20%
Error Correction
20%
Front End
19%
Bit Line
18%
Biosignal
18%
Lookup Table
18%
Voltage Scaling
18%
Coding Scheme
18%
Liquid Phase Epitaxy
18%
Inverter
18%
Dielectrics
18%
Memory Array
17%
Decoupling Capacitor
16%
Analog Front
16%
Data Retention
16%
Technology Integration
16%
Substrate Temperature
16%
Noise Suppression
16%
Network Application
15%
Analog-to-Digital Converter
15%
Signal Acquisition
14%
Application of Sensors
12%
Linear Voltage Regulator
12%
Thermal Sensor
12%
Memory Interface
12%
Network-on-Chip
12%
Modulation Scheme
12%
Silicon Single Crystal
12%
Channel Response
12%
Quadrature Phase Shift Keying
12%
Deep Neural Network
12%
Computer Science
Energy Efficient
100%
Energy Efficiency
36%
Convolutional Neural Network
32%
ternary content addressable memory
31%
Power Consumption
29%
Field Programmable Gate Arrays
26%
Networks on Chips
24%
Deep Neural Network
21%
Computer Hardware
21%
Error Correction
20%
Energy Consumption
20%
First-in-First-Out
18%
Input/Output
18%
Packaging Technology
18%
Design Exploration
18%
IoT Application
15%
High Throughput
14%
Participatory Design
14%
Deep Convolutional Neural Networks
14%
Table Lookup
14%
Deep Learning Method
14%
System-on-Chip
13%
Resource Utilisation
12%
multi sensor
12%
Accelerator Memory
12%
Data Converter
12%
Silicon Interposers
12%
Modulation Scheme
12%
Channel Response
12%
Interconnection Network
12%
Processing Element
10%
Spread Spectrum
10%
Memory Design
10%
Orthogonal Frequency Division Multiplexing
9%
Interconnection Architecture
8%
Carrier Frequency
8%
Workload Distribution
7%
Random Access Memory
7%
Network Application
7%
Clock Frequency
7%
through silicon vias
7%
Notch Frequency
7%
Floating Point
7%
Memory Array
6%
Leakage Current
6%
build-in self-test
6%
Content-Addressable Memory
6%
Neural Network Application
6%
Bitline
6%
wireless local area network
6%
