每年專案
個人檔案
研究專長
數位積體電路設計,記憶體電路及記憶體系統設計,人工智慧加速電路, 三維電路設計
教育/學術資格
PhD, 電子工程, 國立陽明交通大學
外部位置
指紋
查看啟用 Po-Tsang Huang 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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過去五年中的合作和熱門研究領域
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料,或
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利用記憶體內運算及三維記憶體電路實現精度可調深度神經網路
Huang, P.-T. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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教育部智慧晶片系統與應用人才培育計畫--111年度智慧晶片系統與應用跨校教學聯盟計畫-模組教材發展計畫-近記憶體運算及記憶體內運算電路設計
Huang, P.-T. (PI)
1/04/22 → 31/03/23
研究計畫: Ministry of Education(Include School)
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利用記憶體內運算及三維記憶體電路實現精度可調深度神經網路
Huang, P.-T. (PI)
1/08/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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教育部智慧晶片系統與應用人才培育計畫--110年度智慧晶片系統與應用跨校教學聯盟-模組教材發展計畫-近記憶體運算及記憶體內運算電路設計
Huang, P.-T. (PI)
1/07/21 → 31/03/22
研究計畫: Ministry of Education(Include School)
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利用記憶體內運算及三維記憶體電路實現精度可調深度神經網路
Huang, P.-T. (PI)
1/08/20 → 31/07/21
研究計畫: Other Government Ministry Institute
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Continuous single-crystal germanium films using elevated-laser-liquid-phase-epitaxy technique for monolithic 3D integration
Pan, Y. M., Chiu, H. Y., Lin, N. C., Chung, H. T., Wang, C. Y., Chen, C. L., Shih, B. J., Yang, C. C., Huang, P. T., Shen, C. H., Sung, P. J., Wu, W. F., Chen, K. N. & Hu, C., 1 4月 2025, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 64, 4, 04SP56.研究成果: Article › 同行評審
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Surface characteristics optimization during wafer-level backside silicon removal for SOI wafers in 3D integration
Shih, B. J., Chen, Z. Y., Chang, S. P., Chen, T. Y., Sung, P. J., Lin, N. C., Yang, C. C., Huang, P. T., Cheng, H. C., Li, M. Y., Radu, I. P. & Chen, K. N., 15 4月 2025, 於: Applied Surface Science. 688, 162366.研究成果: Article › 同行評審
1 引文 斯高帕斯(Scopus) -
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25 × 33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi
Shih, B. J., Pan, Y. M., Chung, H. T., Lee, C. L., Hsieh, I. C., Lin, N. C., Yang, C. C., Huang, P. T., Chen, H. M., Wang, C. Y., Chiu, H. Y., Cheng, H. C., Shen, C. H., Wu, W. F., Hou, T. H., Chen, K. N. & Hu, C., 2024, 2024 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2024. Institute of Electrical and Electronics Engineers Inc., (Digest of Technical Papers - Symposium on VLSI Technology).研究成果: Conference contribution › 同行評審
1 引文 斯高帕斯(Scopus) -
A 28nm 343.5fps/W Vision Transformer Accelerator with Integer-Only Quantized Attention Block
Lin, C. C., Lu, W., Huang, P. T. & Chen, H. M., 2024, 2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., p. 80-84 5 p. (2024 IEEE 6th International Conference on AI Circuits and Systems, AICAS 2024 - Proceedings).研究成果: Conference contribution › 同行評審
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A 28nm Energy-Area-Efficient Row-based pipelined Training Accelerator with Mixed FXP4/FP16 for On-Device Transfer Learning
Lu, W., Pei, H. H., Yu, J. R., Chen, H. M. & Huang, P. T., 2024, ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).研究成果: Conference contribution › 同行評審
1 引文 斯高帕斯(Scopus)