Pin Su

每年研究成果

篩選

2003
A unified model for partial-depletion and full-depletion SOI circuit designs: Using BSIMPD as a foundation
Su, P., Fung, S. K. H., Wyatt, P. W., Wan, H., Chan, M., Niknejad, A. M. & Hu, C.-M., 2003, 於: Proceedings of the Custom Integrated Circuits Conference. p. 241-244 4 p.
研究成果: Conference article › 同行評審
21 引文斯高帕斯（Scopus）
2000
BSIM4 gate leakage model including source-drain partition
Cao, K. M., Lee, W. C., Liu, W., Jin, X., Su, P., Fung, S. K. H., An, J. X., Yu, B. & Hu, C.-M., 2000, 於: Technical Digest - International Electron Devices Meeting. p. 815-818 4 p.
研究成果: Conference article › 同行評審
168 引文斯高帕斯（Scopus）
BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs
Su, P., Fung, S. K. H., Tang, S., Assaderaghi, F. & Hu, C.-M., 2000, 於: Proceedings of the Custom Integrated Circuits Conference. p. 197-200 4 p.
研究成果: Conference article › 同行評審
37 引文斯高帕斯（Scopus）
1998
Dynamic depletion SOI MOSFET model for SPICE
Sinitsky, D., Fung, S., Tang, S., Su, P., Chan, M., Ko, P. & Hu, C.-M., 1998, 於: Digest of Technical Papers - Symposium on VLSI Technology. p. 114-115 2 p.
研究成果: Conference article › 同行評審
9 引文斯高帕斯（Scopus）

蘇 彬