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查看斯高帕斯 (Scopus) 概要
蘇 彬
教授
電子研究所
智慧半導體奈米系統技術研究中心
https://orcid.org/0000-0002-8213-4103
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2275
引文
25
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830
引文
16
h-指數
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269
引文
9
h-指數
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1994 …
2024
每年研究成果
概覽
指紋
網路
計畫
(20)
研究成果
(253)
類似的個人檔案
(6)
指紋
查看啟用 Pin Su 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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Keyphrases
MOSFET
52%
Fin Field-effect Transistor (FinFET)
47%
Ultra-thin Body
41%
Carbon Nanotube Field Effect Transistor (CNTFET)
35%
SRAM Cell
34%
Germanium-on-insulator (GeOI)
34%
Logic Circuit
30%
Ferroelectric Field-effect Transistor (FeFET)
26%
PMOSFET
24%
6T SRAM Cell
20%
Temperature Effect
19%
Work Function Variation
17%
Line Edge Roughness
17%
Tunnel FET
17%
TFET SRAMs
16%
SOI MOSFET
16%
Threshold Voltage
16%
FinFET Devices
16%
Subthreshold SRAM
15%
InGaAs
15%
Uniaxial
15%
NMOSFET
15%
Analytical Solution
15%
Short Channel
15%
Electrostatic Integrity
14%
Subthreshold Swing
14%
Negative Capacitance
13%
Quantum Confinement
13%
Subthreshold
13%
Monolithic 3-D (M3-D)
13%
Silicon-on-insulator
12%
Random Telegraph Noise
12%
Read Static Noise Margin
12%
Transition Metal Dichalcogenides
12%
Strained Devices
12%
Non-volatile Memory
11%
Antiferroelectric
11%
Tri-gate
11%
Ultra-thin SOI
11%
Process Variation
11%
Drain Current
10%
FET Devices
10%
Short Channel Effects
10%
Cell Stability
10%
NWFET
10%
Heteromeric Channel
10%
Induced Variability
10%
Impact Ionization
9%
Self-heating
9%
Quantum Confinement Effect
9%
Engineering
Metal-Oxide-Semiconductor Field-Effect Transistor
100%
Field Effect Transistor
49%
Logic Circuit
27%
Indium Gallium Arsenide
25%
Tunnel Construction
24%
Noise Margin
22%
Edge Roughness
22%
Nanoscale
18%
Field-Effect Transistor
17%
Quantum Confinement
16%
Silicon on Insulator
16%
Current Drain
15%
Temperature Dependence
14%
Axial Strain
13%
Interlayer
13%
Mixed Mode
12%
Frequency Noise
11%
Quantum Confinement Effect
11%
Gate Length
10%
Process Variation
10%
Dielectrics
10%
Tunnel
10%
Nonvolatile Memory
10%
Impact Ionization
9%
Inverter
9%
Circuit Simulation
9%
Body Effect
8%
Random Access Memory
8%
Access Time
8%
SPICE
7%
Floating Body
7%
Isolation Method
7%
Sense Amplifier
7%
Atomistic Simulation
7%
Gate Bias
6%
Simulation Result
6%
Gate Voltage
6%
Channel Length
6%
Electric Field
5%
Radio Frequency
5%
Nanowire
5%
Operating Cell
5%
Dopants
5%
Carrier Mobility
5%
Random Variation
5%
Fin Width
5%
Circuit Design
5%
Lookup Table
5%
Gate Dielectric
5%