個人檔案
研究專長
矽奈米電子、半導體元件物理、元件模型及設計
經歷
2003/08~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, 電機工程, University of California, Berkeley
外部位置
指紋
查看啟用 Pin Su 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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過去五年中的合作和熱門研究領域
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
專案
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次奈米節點鐵電電晶體關鍵技術：鐵電反鐵電材料與物理,低能耗邏輯與記憶體元件及其高效能運算(2/2)
Su, P. (PI)
1/05/22 → 30/04/23
研究計畫: Other Government Ministry Institute
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次奈米節點鐵電電晶體關鍵技術：鐵電反鐵電材料與物理, 低能耗邏輯與記憶體元件及其高效能運算(1/2)
Su, P. (PI)
1/05/21 → 30/04/22
研究計畫: Other Government Ministry Institute
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A Novel Logic-Compatible and Energy-Efficient Capacitorless DRAM Using CFETs
Semwal, S. & Su, P., 2026, 於: IEEE Transactions on Electron Devices. 73, 1, p. 297-303 7 p.研究成果: Article › 同行評審
1 引文 斯高帕斯（Scopus） -
Electrically Configured Analog Signal Modulation and Logic Operation with Dual-Doped RFET
Semwal, S., Su, P. & Kranti, A., 2026, (Accepted/In press) 於: IEEE Transactions on Nanotechnology.研究成果: Article › 同行評審
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Enabling Broader Memory Windows by Double-Gate Nanosheet Ferroelectric FETs for Next-Generation Non-Volatile Memory Storage
Wu, F., Chiu, C. Y., Lin, T. Y., Wu, C. H., Hu, V. P. H., Su, P. & Su, C. J., 2025, 9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025. Institute of Electrical and Electronics Engineers Inc., (9th IEEE Electron Devices Technology and Manufacturing Conference: Shaping the Future with Innovations in Devices and Manufacturing, EDTM 2025).研究成果: Conference contribution › 同行評審
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Enhancing Analog Performance in Ferroelectric Synapses via Independent Double-Gate Nanosheet FeFETs
Wu, F., Chiu, C. Y., Wu, C. H., Hu, V. P. H., Su, P. & Su, C. J., 2025, 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers. Institute of Electrical and Electronics Engineers Inc., (2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers).研究成果: Conference contribution › 同行評審
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Evaluation of In-Memory Logic Computation for Ferroelectric Capacitive Memory
Chang, H. H., Huang, P. T. & Su, P., 2025, 2025 Silicon Nanoelectronics Workshop, SNW 2025. Institute of Electrical and Electronics Engineers Inc., p. 78-79 2 p. (2025 Silicon Nanoelectronics Workshop, SNW 2025).研究成果: Conference contribution › 同行評審