每年專案
個人檔案
研究專長
微/毫米波電路設計、天線/陣列設計、左手物質傳輸線電路設計
經歷
2006/9~2010/12 Graduate Student Researcher,Electrical Engineering Dept., University of California, Los Angeles
2011/3~2015/7 Assistant Professor, Electrical and Computer Engineering Dept., National Chiao Tung University
2015/8~present Associate Professor, Electrical and Computer Engineering Dept., National Chiao Tung University
教育/學術資格
PhD, 電機工程, University of California, Los Angeles
外部位置
指紋
- 1 類似的個人檔案
過去五年中的合作和熱門研究領域
專案
- 15 已完成
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用於第五代毫米波全雙工無線通訊之差動及低插損雙工器與多通道雙工器研製
Chi, P.-L. (PI)
1/08/23 → 31/07/24
研究計畫: Other Government Ministry Institute
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用於第五代毫米波全雙工無線通訊之差動及低插損雙工器與多通道雙工器研製
Chi, P.-L. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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用於第五代毫米波全雙工無線通訊之差動及低插損雙工器與多通道雙工器研製
Chi, P.-L. (PI)
1/08/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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用於第五代毫米波通訊之差動、低損耗、及雙頻濾波功率分配器與四通道雙工器研製
Chi, P.-L. (PI)
1/08/20 → 31/07/21
研究計畫: Other Government Ministry Institute
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用於第五代毫米波行動通訊之雙頻、差動、及低差損之前端元件研製
Chi, P.-L. (PI)
1/08/19 → 31/07/20
研究計畫: Other Government Ministry Institute
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A 1.9-18-GHz Filter Bank with Improved Passband Flatness Based on Asymmetrical Low-Loss SP7T Switch
Zhu, B., Zhu, X., Li, X., Chi, P. L. & Yang, T., 2025, 於: IEEE Transactions on Microwave Theory and Techniques. 73, 3, p. 1345-1355 11 p.研究成果: Article › 同行評審
4 引文 斯高帕斯(Scopus) -
A 10–17 GHz Continuously Tunable CMOS Filter With Flexible Bandwidth Control Based on Mode-Switching Inductors
Liu, B., Li, K., Chen, Z., Ning, Y., Shao, S., Chi, P. L. & Yang, T., 2025, 於: IEEE Microwave and Wireless Technology Letters. 35, 6, p. 816-819 4 p.研究成果: Article › 同行評審
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A 16-34 GHz CMOS Reconfigurable Bandpass Filter Using Mode-Switching Transformer
Li, K., Liu, B., Zhang, T., Chi, P. L. & Yang, T., 2025, 於: IEEE Transactions on Microwave Theory and Techniques. 73, 3, p. 1516-1531 16 p.研究成果: Article › 同行評審
4 引文 斯高帕斯(Scopus) -
A 2-18-GHz Reconfigurable Low-Noise Amplifier With 2.45-3.4-dB NF in 65-nm CMOS
Liu, J., Wu, S., Li, K., Chi, P. L. & Yang, T., 2025, 於: IEEE Transactions on Microwave Theory and Techniques. 73, 3, p. 1305-1318 14 p.研究成果: Article › 同行評審
7 引文 斯高帕斯(Scopus) -
A 2–15 GHz 6-bit CMOS True Time Delay Chip With High Area Efficiency and Reduced Insertion Loss Variation
Wei, Z., Liu, J., Zhu, X., Chi, P. L., Xu, R., Shao, H. & Yang, T., 2025, 於: IEEE Transactions on Microwave Theory and Techniques. 73, 8, p. 5192-5202 11 p.研究成果: Article › 同行評審
2 引文 斯高帕斯(Scopus)