Ming-Dou Ker

2004

On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process

Ker, M-D., Lin, K. H. & Chuang, C. H., 1 10月 2004, 於: IEEE Transactions on Electron Devices. 51, 10, p. 1628-1635 8 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-μm fully salicided CMOS process

Ker, M-D. & Chen, Z. P., 1 10月 2004, 於: IEEE Transactions on Electron Devices. 51, 10, p. 1731-1733 3 p.

研究成果: Article › 同行評審

28 引文斯高帕斯（Scopus）

2003

Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process

Chen, T. Y. & Ker, M-D., 1 8月 2003, 於: IEEE Transactions on Semiconductor Manufacturing. 16, 3, p. 486-500 15 p.

研究成果: Article › 同行評審

16 引文斯高帕斯（Scopus）

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Lin, I. C., Huang, C. Y., Chao, C. J. & Ker, M-D., 1 8月 2003, 於: Microelectronics Reliability. 43, 8, p. 1295-1301 7 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

CMOS chip as luminescent sensor for biochemical reactions

Lu, U., Hu, B. C. P., Shih, Y. C., Yang, Y-S., Wu, C-Y., Yuan, C-J., Ker, M-D., Wu, T-K., Li, Y-K., Hsieh, Y-Z., Hsu, W-S. & Lin, C. T., 1 6月 2003, 於: IEEE Sensors Journal. 3, 3, p. 310-316 7 p.

研究成果: Article › 同行評審

25 引文斯高帕斯（Scopus）

Dummy-Gate Structure to Improve Turn-on Speed of Silicon-Controlled Rectifier (SCR) Device for Effective Electrostatic Discharge (ESD) Protection

Ker, M-D. & Hsu, K. C., 15 11月 2003, 於: Japanese Journal of Applied Physics, Part 2: Letters. 42, 11 B, p. L1366-L1368

研究成果: Article › 同行評審

ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness

Ker, M-D., Hsu, H. C. & Peng, J. J., 1 10月 2003, 於: IEEE Transactions on Electron Devices. 50, 10, p. 2126-2134 9 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology

Ker, M-D. & Chang, C. Y., 6月 2003, 於: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 42, 6 A, p. 3377-3378 2 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

Ker, M-D. & Hsu, K. C., 1 8月 2003, 於: IEEE Journal of Solid-State Circuits. 38, 8, p. 1380-1392 13 p.

研究成果: Article › 同行評審

43 引文斯高帕斯（Scopus）

Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology

Ker, M-D. & Lo, W. Y., 1 5月 2003, 於: IEEE Transactions on Semiconductor Manufacturing. 16, 2, p. 319-334 16 p.

研究成果: Article › 同行評審

26 引文斯高帕斯（Scopus）

SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes

Ker, M-D. & Hsu, K. C., 1 9月 2003, 於: IEEE Transactions on Device and Materials Reliability. 3, 3, p. 58-68 11 p.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

Substrate-triggered ESD protection circuit without extra process modification

Ker, M-D. & Chen, T. Y., 1 2月 2003, 於: IEEE Journal of Solid-State Circuits. 38, 2, p. 295-302 8 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-μm CMOS process

Ker, M-D. & Hsu, K. C., 1 2月 2003, 於: IEEE Transactions on Electron Devices. 50, 2, p. 397-405 9 p.

研究成果: Article › 同行評審

39 引文斯高帕斯（Scopus）

Substrate-triggered technique for on-chip ESD protection design in a 0.180-μm salicided CMOS process

Ker, M-D. & Chen, T. Y., 1 4月 2003, 於: IEEE Transactions on Electron Devices. 50, 4, p. 1050-1057 8 p.

研究成果: Article › 同行評審

13 引文斯高帕斯（Scopus）

2002

Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications

Ker, M-D., Chen, T. Y. & Wu, C-Y., 1 9月 2002, 於: Analog Integrated Circuits and Signal Processing. 32, 3, p. 257-278 22 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers

Ker, M-D. & Chuang, C. H., 1 8月 2002, 於: IEEE Journal of Solid-State Circuits. 37, 8, p. 1046-1055 10 p.

研究成果: Article › 同行評審

ESD protection circuits with novel MOS-bounded diode structures

Ker, M-D. & Chuang, C. H., 1 1月 2002, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 5, p. V/533-V/536

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness

Ker, M-D., Lo, W. Y., Lee, C. M., Chen, C. P. & Kao, H. S., 1 1月 2002, 於: IEEE MTT-S International Microwave Symposium Digest. 1, p. 537-540 4 p.

研究成果: Article › 同行評審

ESD protection design for CMOS RF integrated circuits using polysilicon diodes

Ker, M-D. & Chang, C. Y., 1 6月 2002, 於: Microelectronics Reliability. 42, 6, p. 863-872 10 p.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs

Ker, M-D. & Peng, J. J., 1 6月 2002, 於: IEEE Transactions on Components and Packaging Technologies. 25, 2, p. 309-316 8 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits

Peng, J. J., Ker, M-D. & Jiang, H. C., 1 1月 2002, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 5, p. V/537-V/540

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit

Ker, M-D. & Chen, T. Y., 1 1月 2002, 於: Journal of Electrostatics. 54, 1, p. 73-93 21 p.

研究成果: Article › 同行評審

Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology

Ker, M-D., Hsu, H. C. & Peng, J. J., 15 11月 2002, 於: Japanese Journal of Applied Physics, Part 2: Letters. 41, 11 B, p. L1288-L1290

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits

Ker, M-D., Chen, T. Y. & Wu, C-Y., 1 5月 2002, 於: Solid-State Electronics. 46, 5, p. 721-734 14 p.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

2001

Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology

Ker, M-D., Jiang, H. C. & Chang, C. Y., 1 12月 2001, 於: IEEE Transactions on Electron Devices. 48, 12, p. 2953-2956 4 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard

Ker, M-D. & Sung, Y. Y., 3月 2001, 於: Microelectronics Reliability. 41, 3, p. 417-429 13 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Investigation of the Gate-Driven Effect and Substrate-Triggered Effect on BSD Robustness of CMOS Devices

Chen, T. Y. & Ker, M-D., 1 12月 2001, 於: IEEE Transactions on Device and Materials Reliability. 1, 4, p. 190-203 14 p.

研究成果: Article › 同行評審

34 引文斯高帕斯（Scopus）

On-chip ESD protection design by using polysilicon diodes in CMOS process

Ker, M-D., Chen, T. Y., Wang, T. H. & Wu, C-Y., 1 4月 2001, 於: IEEE Journal of Solid-State Circuits. 36, 4, p. 676-686 11 p.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

2000

Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger

Ker, M-D. & Chang, H. H., 1 3月 2000, 於: Solid-State Electronics. 44, 3, p. 425-445 21 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Design on the Low-Leakage Diode String for Using in the Power-Rail ESD Clamp Circuits in a 0.35-μm Silicide CMOS Process

Ker, M-D. & Lo, W. Y., 1 4月 2000, 於: IEEE Journal of Solid-State Circuits. 35, 4, p. 601-611 11 p., 839920.

研究成果: Article › 同行評審

46 引文斯高帕斯（Scopus）

ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications

Ker, M-D., Chen, T. Y., Wu, C-Y. & Chang, H. H., 1 8月 2000, 於: IEEE Journal of Solid-State Circuits. 35, 8, p. 1194-1199 6 p., 859509.

研究成果: Article › 同行評審

29 引文斯高帕斯（Scopus）

1999

Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology

Chang, H. H., Ker, M-D. & Wu, J. C., 1 1月 1999, 於: Solid-State Electronics. 43, 2, p. 375-393 19 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on

Ker, M-D. & Chang, H. H., 1 1月 1999, 於: Journal of Electrostatics. 47, 4, p. 215-248 34 p.

研究成果: Article › 同行評審

17 引文斯高帕斯（Scopus）

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness

Ker, M-D., Chen, T. Y. & Chang, H. H., 1 1月 1999, 於: Microelectronics Reliability. 39, 3, p. 415-424 10 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI

Ker, M-D., 1月 1999, 於: IEEE Transactions on Electron Devices. 46, 1, p. 173-183 11 p., 737457.

研究成果: Article › 同行評審

83 引文斯高帕斯（Scopus）

1998

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

Ker, M-D., 1 1月 1998, 於: Microelectronics Reliability. 38, 4, p. 619-639 21 p.

研究成果: Article › 同行評審

ESD protection for slew-rate-controlled output buffer in a 0.5 μm CMOS SRAM technology

Ker, M-D. & Wu, C. N., 1 1月 1998, 於: Solid-State Electronics. 42, 11, p. 2005-2016 12 p.

研究成果: Article › 同行評審

Improved output ESD protection by dynamic gate floating design

Chang, H. H. & Ker, M-D., 1 12月 1998, 於: IEEE Transactions on Electron Devices. 45, 9, p. 2076-2078 3 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Lateral SCR devices with low-voltage high-current triggering characteristics for output ESD protection in submicron CMOS technology

Ker, M-D., 1 12月 1998, 於: IEEE Transactions on Electron Devices. 45, 4, p. 849-860 12 p., 662790.

研究成果: Article › 同行評審

27 引文斯高帕斯（Scopus）

Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area

Ker, M-D., Wu, C-Y., Huang, C. C. & Chen, T. Y., 1 1月 1998, 於: Solid-State Electronics. 42, 6, p. 1007-1014 8 p.

研究成果: Article › 同行評審

1997

A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's

Ker, M-D., Chang, H. H. & Wu, C-Y., 1 1月 1997, 於: IEEE Journal of Solid-State Circuits. 32, 1, p. 38-50 13 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Area-efficient layout design for CMOS output transistors

Ker, M-D., Wu, C-Y. & Wu, T. S., 1 12月 1997, 於: IEEE Transactions on Electron Devices. 44, 4, p. 635-645 11 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current

Ker, M-D., 1 8月 1997, 於: IEEE Journal of Solid-State Circuits. 32, 8, p. 1293-1296 4 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

ESD protection for output pad with well-coupled field-oxide device in 0.5-/nm CMOS technology

Wu, C. N. & Ker, M-D., 1 12月 1997, 於: IEEE Transactions on Electron Devices. 44, 3, p. 503-505 3 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

Latchup-free fully-protected ESD protection circuit for input pad of submicron CMOS ICs

Ker, M-D. & Wu, T. S., 1 1月 1997, 於: Solid-State Electronics. 41, 9, p. 1329-1336 8 p.

研究成果: Article › 同行評審

1996

Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC

Ker, M-D., Wu, C-Y., Cheng, T. & Chang, H. H., 1 12月 1996, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 4, 3, p. 307-321 15 p.

研究成果: Article › 同行評審

26 引文斯高帕斯（Scopus）

Complementary-LVTSCR BSD protection circuit for submicron CMOS VLSI/ULSI

Ker, M-D., Wu, C-Y. & Chang, H. H., 1 12月 1996, 於: IEEE Transactions on Electron Devices. 43, 4, p. 580-587 8 p.

研究成果: Article › 同行評審

Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI

Ker, M-D., Wu, C-Y. & Chang, H. H., 1 4月 1996, 於: IEEE Transactions on Electron Devices. 43, 4, p. 588-598 11 p.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

Efficient output ESD protection for 0.5-μm high-speed CMOS sram IC with well-coupled technique

Ker, M-D. & Wu, C. N., 1 1月 1996, 於: Microelectronics Reliability. 36, 11-12 SPEC. ISS., p. 1731-1734 4 p.

研究成果: Article › 同行評審

ESD protection to overcome internal gate-oxide damage on digital-analog interface of mixed-mode CMOS IC's

Ker, M-D. & Yu, T. L., 1 1月 1996, 於: Microelectronics Reliability. 36, 11-12 SPEC. ISS., p. 1727-1730 4 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

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