Ming-Dou Ker

2007

Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits

Chen, S. H. & Ker, M-D., 1 8月 2007, 於: Microelectronics Reliability. 47, 9-11 SPEC. ISS., p. 1502-1505 4 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process

Chen, S. L. & Ker, M-D., 1 1月 2007, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 54, 1, p. 14-18 5 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Bond pad design with low capacitance in CMOS technology for RF applications

Hsiao, Y. W. & Ker, M-D., 1 1月 2007, 於: IEEE Electron Device Letters. 28, 1, p. 68-70 3 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs

Hsu, S. F. & Ker, M-D., 1 4月 2007, 於: IEEE Transactions on Electron Devices. 54, 4, p. 840-851 12 p.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

Fabrication of a miniature CMOS-based optical biosensor

Ho, W. J., Chen, J. S., Ker, M-D., Wu, T-K., Wu, C-Y., Yang, Y-S., Li, Y-K. & Yuan, C-J., 15 6月 2007, 於: Biosensors and Bioelectronics. 22, 12, p. 3008-3013 6 p.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology

Ker, M-D. & Chen, S. H., 1 5月 2007, 於: IEEE Journal of Solid-State Circuits. 42, 5, p. 1158-1167 10 p.

研究成果: Article › 同行評審

28 引文斯高帕斯（Scopus）

New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process

Chen, J. S. & Ker, M-D., 1 9月 2007, 於: IEEE/OSA Journal of Display Technology. 3, 3, p. 309-314 6 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

On-chip ESD protection design for automotive vacuum-fluorescent-display (VFD) driver IC to sustain high ESD stress

Ker, M-D. & Chang, W. J., 1 9月 2007, 於: IEEE Transactions on Device and Materials Reliability. 7, 3, p. 438-445 8 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology

Ker, M-D. & Chang, W. J., 1 1月 2007, 於: Microelectronics Reliability. 47, 1, p. 27-35 9 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology

Chang, W. J. & Ker, M-D., 1 6月 2007, 於: IEEE Transactions on Device and Materials Reliability. 7, 2, p. 324-332 9 p.

研究成果: Article › 同行評審

16 引文斯高帕斯（Scopus）

The impact of gate-oxide breakdown on common-source amplifiers with diode-connected active load in low-voltage CMOS processes

Chen, J. S. & Ker, M-D., 1 11月 2007, 於: IEEE Transactions on Electron Devices. 54, 11, p. 2860-2870 11 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Transient-induced latchup dependence on power-pin damping frequency and damping factor in CMOS integrated circuits

Hsu, S. F. & Ker, M-D., 1 8月 2007, 於: IEEE Transactions on Electron Devices. 54, 8, p. 2002-2010 9 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes with Polysilicon Diodes

Ker, M-D. & Chen, S. L., 1 1月 2007, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 54, 1, p. 47-51 5 p.

研究成果: Article › 同行評審

13 引文斯高帕斯（Scopus）

2006

BSD-protection design with extra low-leakage-current diode string for RF circuits in SiGe BiCMOS process

Ker, M-D., Hsiao, Y. W. & Wu, W. L., 1 12月 2006, 於: IEEE Transactions on Device and Materials Reliability. 6, 4, p. 517-527 11 p.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations

Ker, M-D. & Hsu, S. F., 1 9月 2006, 於: IEEE Transactions on Device and Materials Reliability. 6, 3, p. 461-472 12 p., 1717497.

研究成果: Article › 同行評審

35 引文斯高帕斯（Scopus）

Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes

Ker, M-D., Chen, S. L. & Tsai, C. S., 1 5月 2006, 於: IEEE Journal of Solid-State Circuits. 41, 5, p. 1100-1107 8 p.

研究成果: Article › 同行評審

186 引文斯高帕斯（Scopus）

Design of mixed-voltage I/O buffer by using NMOS-blocking technique

Ker, M-D. & Chen, S. L., 1 10月 2006, 於: IEEE Journal of Solid-State Circuits. 41, 10, p. 2324-2333 10 p., 1703687.

研究成果: Article › 同行評審

34 引文斯高帕斯（Scopus）

Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

Ker, M-D., Chen, W. Y. & Hsu, K. C., 1 10月 2006, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 53, 10, p. 2187-2193 7 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board

Lin, K. H. & Ker, M-D., 1 2月 2006, 於: Microelectronics Reliability. 46, 2-4, p. 301-310 10 p.

研究成果: Article › 同行評審

ESD failure mechanisms of analog I/O cells in 0.18-μm CMOS technology

Ker, M-D., Chen, S. H. & Chuang, C. H., 1 3月 2006, 於: IEEE Transactions on Device and Materials Reliability. 6, 1, p. 102-111 10 p.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

ESD robustness of thin-film devices with different layout structures in LTPS technology

Deng, C. K. & Ker, M-D., 1 12月 2006, 於: Microelectronics Reliability. 46, 12, p. 2067-2073 7 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test

Ker, M-D. & Hsu, S. F., 1 2月 2006, 於: IEEE Transactions on Electromagnetic Compatibility. 48, 1, p. 161-171 11 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology

Chen, S. H. & Ker, M-D., 1 7月 2006, 於: Microelectronics Reliability. 46, 7, p. 1042-1049 8 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation

Ker, M-D. & Chen, J. S., 1 1月 2006, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 53, 8, p. 667-671 5 p.

研究成果: Article › 同行評審

52 引文斯高帕斯（Scopus）

On-panel output buffer with offset compensation technique for data driver in LTPS technology

Ker, M-D., Deng, C. K. & Huang, J. L., 1 6月 2006, 於: IEEE/OSA Journal of Display Technology. 2, 2, p. 153-158 6 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Optimization of broadband RF performance and ESD robustness by π-model distributed ESD protection scheme

Ker, M-D., Kuo, B. J. & Hsiao, Y. W., 1 2月 2006, 於: Journal of Electrostatics. 64, 2, p. 80-87 8 p.

研究成果: Article › 同行評審

16 引文斯高帕斯（Scopus）

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations

Ker, M-D. & Lin, K. H., 1 12月 2006, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 53, 2, p. 235-246 12 p.

研究成果: Article › 同行評審

26 引文斯高帕斯（Scopus）

Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices

Ker, M-D. & Chen, J. H., 1 11月 2006, 於: IEEE Journal of Solid-State Circuits. 41, 11, p. 2601-2609 9 p., 1717682.

研究成果: Article › 同行評審

45 引文斯高帕斯（Scopus）

2005

A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device

Ker, M-D., Chen, J. S. & Chu, C. Y., 1 11月 2005, 於: IEICE Transactions on Electronics. E88-C, 11, p. 2150-2154 5 p.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

A New Schmitt Trigger Circuit in a 0.13-μm 1/2.5-V CMOS Process to Receive 3.3-V Input Signals

Chen, S. L. & Ker, M-D., 5 7月 2005, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 52, 7, p. 361-365 5 p.

研究成果: Article › 同行評審

50 引文斯高帕斯（Scopus）

Decreasing-size distributed ESD protection scheme for broad-band RF circuits

Ker, M-D. & Kuo, B. J., 1 2月 2005, 於: IEEE Transactions on Microwave Theory and Techniques. 53, 2, p. 582-589 8 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

ESD implantations for on-chip ESD protection with layout consideration in 0.18-μm salicided CMOS technology

Ker, M-D., Chuang, C. H. & Lo, W. Y., 1 5月 2005, 於: IEEE Transactions on Semiconductor Manufacturing. 18, 2, p. 328-337 10 p.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

ESD protection design for 1- To 10-GHz distributed amplifier in CMOS technology

Ker, M-D., Hsiao, Y. W. & Kuo, B. J., 1 9月 2005, 於: IEEE Transactions on Microwave Theory and Techniques. 53, 9, p. 2672-2681 10 p.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology

Ker, M-D. & Lin, K. H., 1 11月 2005, 於: IEEE Journal of Solid-State Circuits. 40, 11, p. 2329-2338 10 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit

Ker, M-D. & Hsu, H. C., 1 1月 2005, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 52, 1, p. 44-53 10 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS

Ker, M-D. & Chang, W. J., 1 9月 2005, 於: IEEE Transactions on Device and Materials Reliability. 5, 3, p. 602-612 11 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Investigation on seal-ring rules for IC product reliability in 0.25-μm CMOS technology

Chen, S. H. & Ker, M-D., 1 9月 2005, 於: Microelectronics Reliability. 45, 9-11, p. 1311-1316 6 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process

Ker, M-D., Lin, K. H. & Chuang, C. H., 1 1月 2005, 於: IEICE Transactions on Electronics. E88-C, 3, p. 429-436 8 p.

研究成果: Article › 同行評審

Native-NMOS-triggered SCR with faster turn-on speed for effective ESD protection in a 0.13-μm CMOS process

Ker, M-D. & Hsu, K. C., 1 9月 2005, 於: IEEE Transactions on Device and Materials Reliability. 5, 3, p. 543-553 11 p.

研究成果: Article › 同行評審

19 引文斯高帕斯（Scopus）

Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits

Ker, M-D. & Hsu, K. C., 1 6月 2005, 於: IEEE Transactions on Device and Materials Reliability. 5, 2, p. 235-249 15 p.

研究成果: Article › 同行評審

141 引文斯高帕斯（Scopus）

Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test

Ker, M-D. & Hsu, S. F., 1 8月 2005, 於: IEEE Transactions on Electron Devices. 52, 8, p. 1821-1831 11 p.

研究成果: Article › 同行評審

57 引文斯高帕斯（Scopus）

SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

Ker, M-D. & Hsu, K. C., 1 5月 2005, 於: IEEE Transactions on Semiconductor Manufacturing. 18, 2, p. 320-327 8 p.

研究成果: Article › 同行評審

29 引文斯高帕斯（Scopus）

The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs

Ker, M-D. & Lin, K. H., 1 8月 2005, 於: IEEE Journal of Solid-State Circuits. 40, 8, p. 1751-1759 9 p.

研究成果: Article › 同行評審

47 引文斯高帕斯（Scopus）

2004

Abnormal ESD Failure Mechanism in High-Pin-Count BGA Packaged ICs Due to Stressing Nonconnected Balls

Lo, W. Y. & Ker, M-D., 1 3月 2004, 於: IEEE Transactions on Device and Materials Reliability. 4, 1, p. 24-31 8 p.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

Active Electrostatic Discharge (ESD) Device for On-Chip ESD Protection in Sub-Quarter-Micron Complementary Metal-Oxide Semiconductor (CMOS) Process

Ker, M-D. & Tseng, T. K., 15 1月 2004, 於: Japanese Journal of Applied Physics, Part 2: Letters. 43, 1 A/B

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Design on ESD protection scheme for IC with power-down-mode operation

Ker, M-D. & Lin, K. H., 1 8月 2004, 於: IEEE Journal of Solid-State Circuits. 39, 8, p. 1378-1382 5 p.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Design optimization of ESD protection and latchup prevention for a serial I/O IC

Huang, C. Y., Chen, W. F., Chuan, S. Y., Chiu, F. C., Tseng, J. C., Lin, I. C., Chao, C. J., Leu, L. Y. & Ker, M-D., 1 2月 2004, 於: Microelectronics Reliability. 44, 2, p. 213-221 9 p.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

Double snapback characteristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design

Ker, M-D. & Lin, K. H., 1 9月 2004, 於: IEEE Electron Device Letters. 25, 9, p. 640-642 3 p.

研究成果: Article › 同行評審

36 引文斯高帕斯（Scopus）

ESD protection design to overcome internal damage on interface circuits of a CMOS IC with multiple separated power pins

Ker, M-D., Chang, C. Y. & Chang, Y. S., 1 9月 2004, 於: IEEE Transactions on Components and Packaging Technologies. 27, 3, p. 445-451 7 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications

Ker, M-D. & Peng, J. J., 1 9月 2004, 於: IEEE Transactions on Components and Packaging Technologies. 27, 3, p. 452-460 9 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

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