Ming-Dou Ker

2017

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

Chen, J. T., Lin, C. Y. & Ker, M-D., 1 10月 2017, 於: IEEE Transactions on Electron Devices. 64, 10, p. 3979-3985 7 p., 8008837.

研究成果: Article › 同行評審

22 引文斯高帕斯（Scopus）

Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process

Luo, Z., Ker, M-D., Cheng, W. H. & Yen, T. Y., 1 3月 2017, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 64, 3, p. 528-536 9 p., 7795238.

研究成果: Article › 同行評審

20 引文斯高帕斯（Scopus）

System-Level ESD Protection for Automotive Electronics by Co-Design of TVS and CAN Transceiver Chips

Chuang, C. H. & Ker, M-D., 1 9月 2017, 於: IEEE Transactions on Device and Materials Reliability. 17, 3, p. 570-576 7 p., 8006249.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

2016

A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process

Luo, Z. & Ker, M-D., 1 12月 2016, 於: IEEE Transactions on Biomedical Circuits and Systems. 10, 6, p. 1087-1099 13 p., 7440898.

研究成果: Article › 同行評審

33 引文斯高帕斯（Scopus）

Area-efficient and low-leakage diode string for On-Chip ESD protection

Lin, C. Y., Wu, P. H. & Ker, M-D., 1 2月 2016, 於: IEEE Transactions on Electron Devices. 63, 2, p. 531-536 6 p., 7353163.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

ESD protection design with stacked high-holding-voltage SCR for high-voltage pins in a battery-monitoring IC

Dai, C. T. & Ker, M-D., 1 5月 2016, 於: IEEE Transactions on Electron Devices. 63, 5, p. 1996-2002 7 p., 7446328.

研究成果: Article › 同行評審

23 引文斯高帕斯（Scopus）

Investigation of Human-Body-Model and Machine-Model ESD Robustness on Stacked Low-Voltage Field-Oxide Devices for High-Voltage Applications

Huang, Y. J. & Ker, M-D., 1 1月 2016, 於: IEEE Transactions on Electron Devices. 63, 8, p. 3193-3198 6 p., 7505894.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process

Lin, C. Y., Wu, Y. H. & Ker, M-D., 1 11月 2016, 於: IEEE Electron Device Letters. 37, 11, p. 1387-1390 4 p.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

Low-leakage bidirectional SCR with symmetrical trigger circuit for ESD protection in 40-nm CMOS process

Altolaguirre, F. A. & Ker, M-D., 1 12月 2016, 於: IEEE Transactions on Device and Materials Reliability. 16, 4, p. 549-555 7 p., 7543508.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 v DDDMOS Process

Dai, C. T. & Ker, M-D., 1 6月 2016, 於: IEEE Transactions on Electron Devices. 63, 6, p. 2449-2454 6 p., 7458868.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

Quad-SCR Device for Cross-Domain ESD Protection

Altolaguirre, F. A. & Ker, M-D., 1 1月 2016, 於: IEEE Transactions on Electron Devices. 63, 8, p. 3177-3184 8 p., 7498685.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

2015

Area-efficient ESD clamp circuit with a capacitance-boosting technique to minimize standby leakage current

Altolaguirre, F. A. & Ker, M-D., 1 1月 2015, 於: IEEE Transactions on Device and Materials Reliability. 15, 2, p. 156-162 7 p., 7050329.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

Latch-up protection design with corresponding complementary current to suppress the effect of external current triggers

Tsai, H. W. & Ker, M-D., 1 1月 2015, 於: IEEE Transactions on Device and Materials Reliability. 15, 2, p. 242-249 8 p., 2424377.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

2014

Active guard ring to improve latch-up immunity

Tsai, H. W. & Ker, M-D., 1 12月 2014, 於: IEEE Transactions on Electron Devices. 61, 12, p. 4145-4152 8 p., 6937197.

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

A fully integrated 8-channel closed-loop neural-prosthetic cmos soc for real-time epileptic seizure control

Chen, W. M., Chiueh, H-M., Chen, T. J., Ho, C. L., Jeng, C., Ker, M-D., Lin, C. Y., Huang, Y. C., Chou, C. W., Fan, T. Y., Cheng, M. S., Hsin, Y. L., Liang, S. F., Wang, Y. L., Shaw, F. Z., Huang, Y. H., Yang, C. H. & Wu, C-Y., 1 1月 2014, 於: IEEE Journal of Solid-State Circuits. 49, 1, p. 232-247 16 p., 6637111.

研究成果: Article › 同行評審

173 引文斯高帕斯（Scopus）

Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-μm CMOS process

Lin, C. Y., Li, Y. J. & Ker, M-D., 1 1月 2014, 於: Analog Integrated Circuits and Signal Processing. 79, 2, p. 219-226 8 p.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Evaluation of subcortical grey matter abnormalities in patients with MRI-negative cortical epilepsy determined through structural and tensor magnetic resonance imaging

Peng, S. J., Harnod, T., Tsai, J. Z., Ker, M-D., Chiou, J-C., Chiueh, H-M., Wu, C-Y. & Hsin, Y. L., 14 5月 2014, 於: BMC Neurology. 14, 1, 104.

研究成果: Article › 同行評審

開啟存取

23 引文斯高帕斯（Scopus）

Investigating electron depletion effect in amorphous indium-gallium-zinc- oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction

Lu, T. C., Chen, W. T., Zan, H-W. & Ker, M-D., 6月 2014, 於: Japanese journal of applied physics. 53, 6, 064302.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Layout consideration and circuit solution to prevent EOS failure induced by latchup test in a high-voltage integrated circuits

Tsai, H. W. & Ker, M-D., 1 1月 2014, 於: IEEE Transactions on Device and Materials Reliability. 14, 1, p. 493-498 6 p., 6226839.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Local CDM ESD protection circuits for cross-power domains in 3D IC applications

Chen, S. H., Linten, D., Scholz, M., Huang, Y. C., Hellings, G., Boschke, R., Ker, M-D. & Groeseneken, G., 1 1月 2014, 於: IEEE Transactions on Device and Materials Reliability. 14, 2, p. 781-783 3 p., 6807728.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit

Chiu, P. Y. & Ker, M-D., 1 1月 2014, 於: Microelectronics Reliability. 54, 1, p. 64-70 7 p.

研究成果: Article › 同行評審

25 引文斯高帕斯（Scopus）

On-chip transient voltage suppressor integrated with silicon-based transceiver IC for system-level ESD protection

Chuang, C. H. & Ker, M-D., 1 1月 2014, 於: IEEE Transactions on Industrial Electronics. 61, 10, p. 5615-5621 7 p., 6701176.

研究成果: Article › 同行評審

13 引文斯高帕斯（Scopus）

On the design of power-rail ESD clamp circuits with gate leakage consideration in nanoscale CMOS technology

Ker, M-D. & Yeh, C. T., 1 1月 2014, 於: IEEE Transactions on Device and Materials Reliability. 14, 1, p. 536-544 9 p., 6587810.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance

Ker, M-D., Lin, W. Y. & Yen, C. C., 1 1月 2014, 於: Microelectronics Reliability. 54, 1, p. 71-78 8 p.

研究成果: Article › 同行評審

Synthesis of uniform core-shell gelatin-alginate microparticles as intestine-released oral delivery drug carrier

Huang, K. S., Yang, C. H., Kung, C. P., Grumezescu, A. M., Ker, M-D., Lin, Y. S. & Wang, C. Y., 1 1月 2014, 於: Electrophoresis. 35, 2-3, p. 330-336 7 p.

研究成果: Article › 同行評審

23 引文斯高帕斯（Scopus）

Through diffusion tensor magnetic resonance imaging to evaluate the original properties of neural pathways of patients with partial seizures and secondary generalization by individual anatomic reference atlas

Peng, S. J., Harnod, T., Tsai, J. Z., Huang, C. C., Ker, M-D., Chiou, J-C., Chiueh, H-M., Wu, C-Y. & Hsin, Y. L., 1 1月 2014, 於: BioMed Research International. 2014, 419376.

研究成果: Article › 同行評審

開啟存取

4 引文斯高帕斯（Scopus）

2013

A latchup-immune and robust SCR device for ESD protection in 0.25-μ m 5-V CMOS process

Huang, Y. C. & Ker, M-D., 5 4月 2013, 於: IEEE Electron Device Letters. 34, 5, p. 674-676 3 p., 6491440.

研究成果: Article › 同行評審

32 引文斯高帕斯（Scopus）

Design of 2 \times {\rm V}_{\rm DD}-Tolerant I/O Buffer with PVT Compensation Realized by only 1 \times {\rm V}_{\rm DD} Thin-Oxide Devices

Ker, M-D. & Chiu, P. Y., 7 10月 2013, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 60, 10, p. 2549-2560 12 p., 6609128.

研究成果: Article › 同行評審

26 引文斯高帕斯（Scopus）

Design of dual-band ESD protection for 24-/60-GHz millimeter-wave circuits

Chu, L. W., Lin, C. Y. & Ker, M-D., 19 3月 2013, 於: IEEE Transactions on Device and Materials Reliability. 13, 1, p. 110-118 9 p., 6296697.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

ESD and EOS impacts during module assembly processes for display panels

Chen, T. Y. & Ker, M-D., 1 1月 2013, 於: Digest of Technical Papers - SID International Symposium. 44, 1, p. 302-305 4 p.

研究成果: Article › 同行評審

High area-efficient ESD clamp circuit with equivalent RC-based detection mechanism in a 65-nm CMOS process

Yeh, C. T. & Ker, M-D., 22 2月 2013, 於: IEEE Transactions on Electron Devices. 60, 3, p. 1011-1018 8 p., 6463443.

研究成果: Article › 同行評審

13 引文斯高帕斯（Scopus）

Implantable stimulator for epileptic seizure suppression with loading impedance adaptability

Lin, C. Y., Chen, W. L. & Ker, M-D., 1 1月 2013, 於: IEEE Transactions on Biomedical Circuits and Systems. 7, 2, p. 196-203 8 p., 6231703.

研究成果: Article › 同行評審

27 引文斯高帕斯（Scopus）

Large-Swing-Tolerant ESD Protection circuit for gigahertz power amplifier in a 65-nm CMOS Process

Lin, C. Y., Tsai, S. Y., Chu, L. W. & Ker, M-D., 1 1月 2013, 於: IEEE Transactions on Microwave Theory and Techniques. 61, 2, p. 914-921 8 p., 6381493.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit

Yeh, C. T. & Ker, M-D., 1 2月 2013, 於: Microelectronics Reliability. 53, 2, p. 208-214 7 p.

研究成果: Article › 同行評審

Power-rail ESD clamp circuit with diode-string ESD detection to overcome the gate leakage current in a 40-nm CMOS process

Altolaguirre, F. A. & Ker, M-D., 12 8月 2013, 於: IEEE Transactions on Electron Devices. 60, 10, p. 3500-3507 8 p., 6575132.

研究成果: Article › 同行評審

35 引文斯高帕斯（Scopus）

Robust ESD protection design for 40-GB/s transceiver in 65-Nm CMOS process

Lin, C. Y., Chu, L. W. & Ker, M-D., 9 9月 2013, 於: IEEE Transactions on Electron Devices. 60, 11, p. 3625-3631 7 p., 6588898.

研究成果: Article › 同行評審

5 引文斯高帕斯（Scopus）

2012

Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology

Lin, C. Y., Chu, L. W., Tsai, S. Y. & Ker, M-D., 14 9月 2012, 於: IEEE Transactions on Device and Materials Reliability. 12, 3, p. 554-561 8 p., 6155079.

研究成果: Article › 同行評審

2 引文斯高帕斯（Scopus）

Diode-triggered silicon-controlled rectifier with reduced voltage overshoot for CDM ESD protection

Chen, W. Y., Rosenbaum, E. & Ker, M-D., 1 3月 2012, 於: IEEE Transactions on Device and Materials Reliability. 12, 1, p. 10-14 5 p., 6163575.

研究成果: Article › 同行評審

35 引文斯高帕斯（Scopus）

ESD protection design for 60-GHz LNA with inductor-triggered SCR in 65-nm CMOS process

Lin, C. Y., Chu, L. W. & Ker, M-D., 1 3月 2012, 於: IEEE Transactions on Microwave Theory and Techniques. 60, 3 PART 2, p. 714-723 10 p., 06129526.

研究成果: Article › 同行評審

21 引文斯高帕斯（Scopus）

Investigation on CDM ESD events at core circuits in a 65-nm CMOS process

Lin, C. Y., Chang, T. L. & Ker, M-D., 1 11月 2012, 於: Microelectronics Reliability. 52, 11, p. 2627-2631 5 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

New 4-Bit transient-to-digital converter for system-level ESD protection in display panels

Ker, M-D. & Yen, C. C., 1 2月 2012, 於: IEEE Transactions on Industrial Electronics. 59, 2, p. 1278-1287 10 p., 5771998.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

New design of 2 × VDD-tolerant power-rail ESD clamp circuit for mixed-voltage I/O buffers in 65-nm CMOS technology

Yeh, C. T. & Ker, M-D., 1 3月 2012, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 59, 3, p. 178-182 5 p., 6153054.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

Power-rail ESD clamp circuit with ultralow standby leakage current and high area efficiency in nanometer CMOS technology

Yeh, C. T. & Ker, M-D., 21 8月 2012, 於: IEEE Transactions on Electron Devices. 59, 10, p. 2626-2634 9 p., 6269072.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

Resistor-less design of power-rail ESD clamp circuit in nanoscale CMOS technology

Yeh, C. T. & Ker, M-D., 1 1月 2012, 於: IEEE Transactions on Electron Devices. 59, 12, p. 3456-3463 8 p., 6335469.

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications

Yeh, C. T. & Ker, M-D., 1 6月 2012, 於: Microelectronics Reliability. 52, 6, p. 1020-1030 11 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

2011

Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process

Lin, C. Y., Chu, L. W. & Ker, M-D., 1 8月 2011, 於: Microelectronics Reliability. 51, 8, p. 1315-1324 10 p.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

Design and implementation of readout circuit on glass substrate with digital correction for touch-panel applications

Wang, T. M. & Ker, M-D., 1 7月 2011, 於: Journal of the Society for Information Display. 19, 7, p. 463-470 8 p.

研究成果: Article › 同行評審

Design of analog pixel memory for low power application in TFT-LCDs

Chu, L. W., Liu, P-T. & Ker, M-D., 31 1月 2011, 於: IEEE/OSA Journal of Display Technology. 7, 2, p. 62-69 8 p., 5695001.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

Design of digital time-modulation pixel memory circuit on glass substrate for low power application

Chen, S. H., Ker, M-D. & Wang, T. M., 1 6月 2011, 於: Digest of Technical Papers - SID International Symposium. 42, 1, p. 1281-1284 4 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Design of integrated gate driver with threshold voltage drop cancellation in amorphous silicon technology for TFT-LCD application

Chu, L. W., Liu, P-T. & Ker, M-D., 31 10月 2011, 於: IEEE/OSA Journal of Display Technology. 7, 12, p. 657-664 8 p., 6052150.

研究成果: Article › 同行評審

41 引文斯高帕斯（Scopus）

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