Ming-Dou Ker

2013

Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process

Huang, Y. C., Dai, C. T. & Ker, M-D., 27 5月 2013, p. 116-119. 4 p.

研究成果: Paper › 同行評審

22 引文斯高帕斯（Scopus）

2012

Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Chu, L. W., Lin, C. Y., Tsai, S. Y., Ker, M-D., Song, M. H., Jou, C. P., Lu, T. H., Tseng, J. C., Tsai, M. H., Hsu, T. L., Hung, P. F. & Chang, T. H., 28 9月 2012, p. 2127-2130. 4 p.

研究成果: Paper › 同行評審

2 引文斯高帕斯（Scopus）

2006

ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffers with 3×VDD input tolerance

Ker, M-D. & Wang, C. T., 1 12月 2006, p. 287-290. 4 p.

研究成果: Paper › 同行評審

7 引文斯高帕斯（Scopus）

2005

A new failure mechanism on analog I/O cell under ND-mode ESD stress in deep-submicron CMOS technology

Chen, S. H., Ker, M-D. & Chuang, C. H., 6月 2005, p. 209-212. 4 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

ESD protection structure with embedded high-voltage P-type SCR for automotive vacuum-fluorescent-display (VFD) applications

Ker, M-D., Chang, W. J., Yang, M., Chen, C. C., Chan, M. C., Shieh, W. T. & Yen, K. L., 6月 2005, p. 67-70. 4 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

2004

Active ESD shunt with transistor feedback to reduce Latchup susceptibility or false triggering

Tong, P. C. F., Chen, W., Ker, M-D., Hui, J., Xu, P. P. & Liu, P. Z. Q., 10月 2004, p. 820-823. 4 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

Characterization on ESD devices with test structures in silicon Germanium RF BiCMOS process

Ker, M-D., Wu, W. L. & Chang, C. Y., 3月 2004, p. 7-12. 6 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCos IC product

Ker, M-D., Chen, S. H. & Tseng, T. K., 1 12月 2004, p. 845-848. 4 p.

研究成果: Paper › 同行評審

Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devices

Ker, M-D., Hou, C. L., Chang, C. Y. & Chu, F. T., 1 12月 2004, p. 209-212. 4 p.

研究成果: Paper › 同行評審

12 引文斯高帕斯（Scopus）

ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme

Ker, M-D. & Kuo, B. J., 6月 2004, p. 383-386. 4 p.

研究成果: Paper › 同行評審

5 引文斯高帕斯（Scopus）

ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

Ker, M-D. & Chuang, C. H., 1 12月 2004, p. 217-220. 4 p.

研究成果: Paper › 同行評審

4 引文斯高帕斯（Scopus）

Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces

Chang, W. J. & Ker, M-D., 7月 2004, p. 213-216. 4 p.

研究成果: Paper › 同行評審

3 引文斯高帕斯（Scopus）

New design concept for on-chip ESD protection circuits with already-on device in nanoscale CMOS technology

Ker, M-D. & Hsu, K. C., 12月 2004, p. 841-844. 4 p.

研究成果: Paper › 同行評審

Test structures to verify ESD robustness of on-glass devices in LTPS technology

Ker, M-D., Deng, C. K., Yang, S. C. & Tasi, Y. M., 3月 2004, p. 13-17. 5 p.

研究成果: Paper › 同行評審

2003

A novel LC-tank ESD protection design for giga-Hz RF circuits

Ker, M-D., Chou, C. I. & Lee, C. M., 6月 2003, p. 115-118. 4 p.

研究成果: Paper › 同行評審

30 引文斯高帕斯（Scopus）

Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOC IC's

Ker, M-D., Peng, J. J. & Jiang, H. C., 3月 2003, p. 161-166. 6 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

2002

ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness

Ker, M-D., Lo, W. Y., Lee, C. M., Chen, C. P. & Kao, H. S., 1 1月 2002, p. 427-430. 4 p.

研究成果: Paper › 同行評審

30 引文斯高帕斯（Scopus）

2001

ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ker, M-D. & Chuang, C. H., 13 7月 2001, p. 85-90. 6 p.

研究成果: Paper › 同行評審

22 引文斯高帕斯（Scopus）

ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

Chen, T. Y. & Ker, M-D., 18 4月 2001, p. 232-235. 4 p.

研究成果: Paper › 同行評審

7 引文斯高帕斯（Scopus）

Investigation on ESD robustness of CMOS devices in a 1.8-V 0.15-μm partially-depleted SOI salicide CMOS technology

Ker, M-D., Hong, K. K., Chen, T. Y., Tang, H., Huang, S. C., Chen, S. S., Huang, C. T., Wang, M. C. & Loh, Y. T., 18 4月 2001, p. 41-44. 4 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

Level shifters for high-speed 1-V to 3.3-V interfaces in a 0.13-μm Cu-interconnection/low-k CMOS technology

Wang, W. T., Ker, M-D., Chiang, M. C. & Chen, C. H., 26 9月 2001, p. 307-310. 4 p.

研究成果: Paper › 同行評審

40 引文斯高帕斯（Scopus）

Novel diode structures and ESD protection circuits in a 1.8-V 0.15-μm partially-depleted SOI salicided CMOS process

Ker, M-D., Hung, K. K., Tang, H. T. H., Huang, S. C., Chen, S. S. & Wang, M. C., 7月 2001, p. 91-96. 6 p.

研究成果: Paper › 同行評審

15 引文斯高帕斯（Scopus）

On-chip ESD protection design for GHz RF integrated circuits by using polysilicon diodes in sub-quarter-micron CMOS process

Chang, C. Y. & Ker, M-D., 4月 2001, p. 240-243. 4 p.

研究成果: Paper › 同行評審

8 引文斯高帕斯（Scopus）

1998

CMOS on-chip ESD protection design with substrate-triggering technique

Ker, M-D., Chen, T. Y. & Wu, C-Y., 1 12月 1998, p. 273-276. 4 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

1997

Advanced layout design for deep-submicron CMOS output buffer with higher driving capability and better ESD reliability

Ker, M-D., Wu, C-Y. & Chen, T. Y., 1 1月 1997, p. 45-49. 5 p.

研究成果: Paper › 同行評審

Area-efficient VDD-to-VSS ESD clamp circuit by using substrate-triggering field-oxide device (STFOD) for whole-chip ESD protection

Ker, M-D., 1 1月 1997, p. 69-73. 5 p.

研究成果: Paper › 同行評審

13 引文斯高帕斯（Scopus）

Efficient output ESD protection of high-speed SRAM IC with well-coupled technique in sub-μm CMOS technology

Wu, C. N., Ker, M-D., Yu, T. L., Lin, S. T., Young, K. L. & Chiu, K. Y., 1 1月 1997, p. 40-44. 5 p.

研究成果: Paper › 同行評審

Layout verification for submicron CMOS cell libraries to improve ESD/latchup reliability

Ker, M-D., Hsiao, S. M. & Lin, J. H., 1 1月 1997, p. 343-347. 5 p.

研究成果: Paper › 同行評審

New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness in per unit layout area

Ker, M-D., Chen, T. Y. & Wu, C-Y., 1 12月 1997, p. 103-108. 6 p.

研究成果: Paper › 同行評審

1 引文斯高帕斯（Scopus）

1996

Area-efficient layout design for output transistors with consideration of ESD reliability

Ker, M-D., Wu, C-Y., Huang, C. C., Chang, H. H., Wu, C. N. & Yu, T. L., 1 12月 1996, p. 94-96. 3 p.

研究成果: Paper › 同行評審

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Ker, M-D., Wu, C-Y., Chang, H. H., Huang, C. C., Wu, C. N. & Yu, T. L., 1 12月 1996, p. 98-101. 4 p.

研究成果: Paper › 同行評審

1995

Efficient layout style of CMOS output buffer to improve driving capability of low-voltage submicron CMOS IC's

Ker, M-D., Wu, C-Y., Cheng, T., Chang, H. H., Wu, M. J. N. & Yu, T. L., 1 12月 1995, p. 193-195. 3 p.

研究成果: Paper › 同行評審

1994

On-chip ESD protection circuit with complementary SCR structures for submicron CMOS ICs

Ker, M-D., Wu, C-Y., Jiang, H. C., Lee, C. Y., Ko, J. & Hsue, P., 1 12月 1994, p. 1145-1148. 4 p.

研究成果: Paper › 同行評審

Whole-chip ESD protection for CMOS VLSI/ULSI with multiple power pins

Ker, M-D., Wu, C-Y., Cheng, T., Wu, M. J. N., Yu, T. L. & Wang, A. C., 1 12月 1994, p. 124-128. 5 p.

研究成果: Paper › 同行評審

8 引文斯高帕斯（Scopus）

柯 明道

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