明道 柯 的照片

查看斯高帕斯 (Scopus) 概要

柯 明道

教授

 https://orcid.org/0000-0003-3622-181X
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1991 …2023

每年研究成果

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篩選
Conference contribution

搜尋結果

  • 2010

    Impact of layout pickups to ESD robustness of MOS transistors in sub 100-nm CMOS process

    Ker, M-D., Wen, Y. R., Chen, W. Y. & Lin, C. Y., 1 12月 2010, 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program. p. 100-103 4 p. 5669188. (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program).

    研究成果: Conference contribution › 同行評審

    11 引文 斯高帕斯（Scopus）

  • Implementation of the cosine law for location awareness system

    Lin, P. J., Huang, Y. C., Huang, Y. J. & Ker, M-D., 20 12月 2010, PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics. p. 255-258 4 p. 5604912. (PrimeAsia 2010 - 2nd Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Layout optimization on ESD diodes for giga-Hz RF and high-speed I/O circuits

    Yeh, C. T., Liang, Y. C. & Ker, M-D., 8 11月 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010. p. 241-244 4 p. 5496734. (Proceedings of 2010 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2010).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Modeling the parasitic capacitance of ESD protection SCR to Co-design matching network in RF ICs

    Lin, C. Y. & Ker, M-D., 1 12月 2010, 2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program. p. 104-107 4 p. 5669189. (2010 International Symposium on Next-Generation Electronics, ISNE 2010 - Conference Program).

    研究成果: Conference contribution › 同行評審

  • New transient detection circuit for Electrical Fast Transient (EFT) protection design in display panels

    Ker, M-D., Lin, W. Y., Yen, C. C., Yang, C. M., Chen, T. Y. & Chen, S. F., 20 8月 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010. p. 51-54 4 p. 5510297. (2010 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2010).

    研究成果: Conference contribution › 同行評審

    6 引文 斯高帕斯（Scopus）

  • On-chip ESD detection circuit for system-level ESD protection design

    Ker, M-D., Lin, W. Y., Yen, C. C., Yang, C. M., Chen, T. Y. & Chen, S. F., 1 12月 2010, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. p. 1584-1587 4 p. 5667447. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

    研究成果: Conference contribution › 同行評審

    9 引文 斯高帕斯（Scopus）

  • Optimized layout on ESD protection diode with low parasitic capacitance

    Yeh, C. T. & Ker, M-D., 1 12月 2010, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. p. 1701-1703 3 p. 5667306. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Protection design against system-level ESD transient disturbance on display panels

    Ker, M-D., Lin, W. Y., Yen, C. C., Yang, C. M., Chen, T. Y. & Chen, S. F., 2 8月 2010, 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010. p. 438-441 4 p. 5475821. (2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010).

    研究成果: Conference contribution › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Self-matched ESD cell in CMOS technology for 60-GHz broadband RF applications

    Lin, C. Y., Chu, L. W., Ker, M-D., Lu, T. H., Hung, P. F. & Li, H. C., 16 7月 2010, Proceedings of the 2010 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2010. p. 573-576 4 p. 10.1109/RFIC.2010.5477291. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

    研究成果: Conference contribution › 同行評審

    14 引文 斯高帕斯（Scopus）
  • 2009

    Chip-level and board-level CDM ESD tests on IC products

    Ker, M-D., Huang, C. K., Hsiao, Y. W. & Hsieh, Y. F., 16 11月 2009, Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009. p. 45-49 5 p. 5232702. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS

    Ker, M-D. & Wang, C. T., 1 12月 2009, 2009 IEEE Custom Integrated Circuits Conference, CICC '09. p. 689-696 8 p. 5280728. (Proceedings of the Custom Integrated Circuits Conference).

    研究成果: Conference contribution › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices

    Ker, M-D. & Lin, Y. L., 1 12月 2009, 2009 IEEE Custom Integrated Circuits Conference, CICC '09. p. 539-542 4 p. 5280763. (Proceedings of the Custom Integrated Circuits Conference).

    研究成果: Conference contribution › 同行評審

    12 引文 斯高帕斯（Scopus）

  • Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition

    Chen, S. H. & Ker, M-D., 1 12月 2009, 2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09. p. 327-330 4 p. 5158161. (2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09).

    研究成果: Conference contribution › 同行評審

    3 引文 斯高帕斯（Scopus）

  • Improvement on ESD robustness of lateral DMOS in high-voltage CMOS ICs by body current injection

    Chen, W. Y., Ker, M-D., Jou, Y. N., Huang, Y. J. & Lin, G. L., 26 10月 2009, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. p. 385-388 4 p. 5117766. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: Conference contribution › 同行評審

    12 引文 斯高帕斯（Scopus）

  • Low-leakage electrostatic discharge protection circuit in 65-nm fully-silicided CMOS technology

    Wang, C. T., Ker, M-D., Tang, T. H. & Su, K. C., 1 12月 2009, 2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009. p. 21-24 4 p. 5166256. (2009 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2009).

    研究成果: Conference contribution › 同行評審

  • New layout scheme to improve ESD robustness of I/O buffers in fully-silicided CMOS process

    Ker, M-D., Chen, W. Y., Shieh, W. T. & Wei, I. J., 11月 2009, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2009, EOS/ESD 2009. 5340148. (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • On the design of power-rail ESD clamp circuit with consideration of gate leakage current in 65-nm low-voltage CMOS process

    Ker, M-D., Chiu, P. Y., Tsai, F. Y. & Chang, Y. J., 26 10月 2009, 2009 IEEE International Symposium on Circuits and Systems, ISCAS 2009. p. 2281-2284 4 p. 5118254. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: Conference contribution › 同行評審

    11 引文 斯高帕斯（Scopus）

  • Source-side engineering to increase holding voltage of LDMOS in a O.5-m 16-V BCD technology to avoid latch-up failure

    Chen, W. Y., Ker, M-D., Jou, Y. N., Huang, Y. J. & Lin, G. L., 16 11月 2009, Proceedings of the 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2009. p. 41-44 4 p. 5232701. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

    研究成果: Conference contribution › 同行評審

    16 引文 斯高帕斯（Scopus）

  • Transient-to-digital converter for protection design in CMOS integrated circuits against electrical fast transient

    Yen, C. C., Ker, M-D., Liao, C. S., Chen, T. Y. & Tsai, C. C., 1 12月 2009, 2009 IEEE International Symposium on Electromagnetic Compatibility, EMC 2009. p. 41-44 4 p. 5284683. (IEEE International Symposium on Electromagnetic Compatibility).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Ultra-low-leakage power-rail ESD clamp circuit in nanoscale low-voltage CMOS process

    Chiu, P. Y., Ker, M-D., Tsai, F. Y. & Chang, Y. J., 12 11月 2009, 2009 IEEE International Reliability Physics Symposium, IRPS 2009. p. 750-753 4 p. 5173343. (IEEE International Reliability Physics Symposium Proceedings).

    研究成果: Conference contribution › 同行評審

    12 引文 斯高帕斯（Scopus）
  • 2008

    2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue

    Ker, M-D., Wang, T. M. & Liao, H. T., 19 9月 2008, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 820-823 4 p. 4541544. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • CDM ESD protection in CMOS integrated circuits

    Ker, M-D. & Hsiao, Y. W., 9月 2008, Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2008, EAMTA. p. 61-66 6 p. 4638978. (Proceedings of the Argentine School of Micro-Nanoelectronics, Technology and Applications 2008, EAMTA).

    研究成果: Conference contribution › 同行評審

    4 引文 斯高帕斯（Scopus）

  • Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process

    Ker, M-D., Wang, T. M. & Hu, F. L., 26 12月 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 1047-1050 4 p. 4675036. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: Conference contribution › 同行評審

    17 引文 斯高帕斯（Scopus）

  • ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR

    Ker, M-D., Lin, C. Y. & Meng, G. X., 19 9月 2008, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. p. 1292-1295 4 p. 4541662. (Proceedings - IEEE International Symposium on Circuits and Systems).

    研究成果: Conference contribution › 同行評審

    3 引文 斯高帕斯（Scopus）

  • ESD protection design for RF circuits in CMOS technology with low-c implementation

    Lin, C. Y. & Ker, M-D., 3月 2008, Semiconductor Technology, ISTC 2008 - Proceedings of the 7th International Conference on Semiconductor Technology. p. 70-75 6 p. (Proceedings - Electrochemical Society; 卷 PV 2008-1).

    研究成果: Conference contribution › 同行評審

  • High-robust ESD protection structure with embedded SCR in high-voltage CMOS process

    Lai, T. H., Ker, M-D., Chang, W. J., Tang, T. H. & Su, K. C., 17 9月 2008, 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS. p. 627-628 2 p. 4558959. (IEEE International Reliability Physics Symposium Proceedings).

    研究成果: Conference contribution › 同行評審

    8 引文 斯高帕斯（Scopus）

  • Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

    Chen, W. Y., Ker, M-D., Huang, Y. J., Jou, Y. N. & Lin, G. L., 1 12月 2008, Proceedings of APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems. p. 61-64 4 p. 4745960. (IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS).

    研究成果: Conference contribution › 同行評審

    13 引文 斯高帕斯（Scopus）

  • Mechanism of snapback failure induced by the latch-up test in high-voltage CMOS integrated circuits

    Tseng, J. C., Chen, Y. L., Hsu, C. T., Tsai, F. Y., Chen, P. A. & Ker, M-D., 17 9月 2008, 46th Annual 2008 IEEE International Reliability Physics Symposium Proceedings, IRPS. p. 625-626 2 p. 4558958. (IEEE International Reliability Physics Symposium Proceedings).

    研究成果: Conference contribution › 同行評審

    3 引文 斯高帕斯（Scopus）

  • New transient detection circuit for system-level ESD protection

    Yen, C. C., Liao, C. S. & Ker, M-D., 5 9月 2008, 2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT. p. 180-183 4 p. 4542442. (2008 International Symposium on VLSI Design, Automation, and Test, VLSI-DAT).

    研究成果: Conference contribution › 同行評審

  • On-glass digital-to-analog converter with gamma correction for panel data driver

    Wang, T. M., Li, Y. H. & Ker, M-D., 26 12月 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 202-205 4 p. 4674826. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: Conference contribution › 同行評審

    5 引文 斯高帕斯（Scopus）

  • Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

    Chen, S. H. & Ker, M-D., 26 12月 2008, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. p. 666-669 4 p. 4674941. (Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008).

    研究成果: Conference contribution › 同行評審

    6 引文 斯高帕斯（Scopus）

  • Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits

    Lin, C. Y. & Ker, M-D., 23 9月 2008, 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 4588154. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

    研究成果: Conference contribution › 同行評審

  • Transient-to-digital converter for ESD protection design in microelectronic systems

    Ker, M-D., Yen, C. C., Liao, C. S., Chen, T. Y. & Tsai, C. C., 1 12月 2008, Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008. p. 409-412 4 p. 4708814. (Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）
  • 2007

    A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes

    Wang, T. M., Shen, W. Y. & Ker, M-D., 1 12月 2007, ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. p. 206-209 4 p. 4510966. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: Conference contribution › 同行評審

  • Automation of synchronous bias transmission line pulsing system

    Chang, B. W., Hsu, H. C. & Ker, M-D., 28 9月 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239446. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Board level ESD of driver ICs on LCD panels

    Hsu, C. T., Tseng, J. C., Chen, Y. L., Tsai, F. Y., Yu, S. H., Chen, P. A. & Ker, M-D., 25 9月 2007, 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual. p. 590-591 2 p. 4227706. (Annual Proceedings - Reliability Physics (Symposium)).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • CMOS power amplifier with ESD protection design merged in matching network

    Shiu, Y. D., Huang, B. S. & Ker, M-D., 1 12月 2007, ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. p. 825-828 4 p. 4511118. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: Conference contribution › 同行評審

    6 引文 斯高帕斯（Scopus）

  • Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation

    Tsai, H. W. & Ker, M-D., 1 12月 2007, ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. p. 1240-1243 4 p. 4511221. (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

    Ker, M-D., Wang, C. T., Tang, T. H. & Su, K. C., 25 9月 2007, 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual. p. 594-595 2 p. 4227708. (Annual Proceedings - Reliability Physics (Symposium)).

    研究成果: Conference contribution › 同行評審

    5 引文 斯高帕斯（Scopus）

  • Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability

    Ker, M-D. & Hu, F. L., 28 9月 2007, 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers. 4239397. (2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers).

    研究成果: Conference contribution › 同行評審

    12 引文 斯高帕斯（Scopus）

  • ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

    Hsiao, Y. W., Ker, M-D., Chiu, P. Y., Huang, C. & Tseng, Y. K., 1 12月 2007, Proceedings - 20th Anniversary IEEE International SOC Conference. p. 277-280 4 p. 4545474. (Proceedings - 20th Anniversary IEEE International SOC Conference).

    研究成果: Conference contribution › 同行評審

  • Failure of on-chip power-rail ESD clamp circuits during system-level ESD test

    Yen, C. C. & Ker, M-D., 25 9月 2007, 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual. p. 598-599 2 p. 4227710. (Annual Proceedings - Reliability Physics (Symposium)).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology

    Chen, J. S. & Ker, M-D., 25 9月 2007, 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual. p. 664-665 2 p. 4227743. (Annual Proceedings - Reliability Physics (Symposium)).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Latehup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test

    Ker, M-D. & Yen, C. C., 1 12月 2007, IEEE International Symposium on Electromagnetic Compatibility, EMC 2007. 4305743. (IEEE International Symposium on Electromagnetic Compatibility).

    研究成果: Conference contribution › 同行評審

  • Low-capaeitance SCR with waffle layout structure for on-chip ESD protection in RF ICs

    Lin, C. Y. & Ker, M-D., 2 10月 2007, Proceedings of the 2007 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2007. p. 749-752 4 p. 4266539. (Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium).

    研究成果: Conference contribution › 同行評審

    12 引文 斯高帕斯（Scopus）

  • On-panel analog output buffer for data driver with consideration of device characteristic variation in LTPS technology

    Li, Y. H., Ker, M-D., Huang, C. Y. & Hsu, C. Y., 3月 2007, AD'07 - Proceedings of Asia Display 2007. p. 210-215 6 p. (AD'07 - Proceedings of Asia Display 2007; 卷 1).

    研究成果: Conference contribution › 同行評審

  • On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process

    Ker, M-D., Chuang, J. Y., Deng, C. K., Kuo, C. H., Li, C. H., Lai, M. S., Wang, C. W. & Liu, C. T., 3月 2007, AD'07 - Proceedings of Asia Display 2007. p. 551-556 6 p. (AD'07 - Proceedings of Asia Display 2007; 卷 1).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）

  • Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-μm CMOS technology

    Chen, S. H. & Ker, M-D., 1 12月 2007, Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. p. 245-248 4 p. 4378093. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

    研究成果: Conference contribution › 同行評審

    2 引文 斯高帕斯（Scopus）

  • Test structure on SCR device in waffle layout for RF ESD protection

    Ker, M-D. & Lin, C. Y., 27 9月 2007, 2007 IEEE International Conference on Microelectronic Test Structures, ICMTS - Conference Proceedings. p. 196-199 4 p. 4252432. (IEEE International Conference on Microelectronic Test Structures).

    研究成果: Conference contribution › 同行評審

    3 引文 斯高帕斯（Scopus）

  • The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process

    Chang, W. J., Ker, M-D., Lai, T. X., Tang, T. H. & Su, K. C., 1 12月 2007, Proceedings of the 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2007. p. 249-252 4 p. 4378094. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

    研究成果: Conference contribution › 同行評審

    1 引文 斯高帕斯（Scopus）