每年專案
個人檔案
研究專長
積體電路設計,積體電路可靠度,生醫電子,智慧型仿生電路與系統,特定應用積體電路與,類比及混合訊號電路,前瞻設計與設計技術,
經歷
2004-2009 國立交通大學電子工程學系/電子研究所 教授
2008-2011 義守大學講座教授
2011-2015 行政院奈米國家型科技計畫執行長
2012-2015 國立交通大學光電學院院長
2010-迄今 國立交通大學特聘教授
2011-迄今 國立交通大學智慧型仿生系統研究中心主任
教育/學術資格
PhD, 電機工程, National Chiao Tung University
外部位置
指紋
- 1 類似的個人檔案
過去五年中的合作和熱門研究領域
專案
- 40 已完成
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無線式可擴增之神經感測與刺激微系統技術平台開發- 多通道多相位刺激器電路設計
Ker, M.-D. (PI)
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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智慧型可適性深腦刺激系統於帕金森氏症精準治療之研究-智慧型可適性深腦刺激系統於帕金森氏症精準治療之研究(2/2)
Ker, M.-D. (PI)
1/01/22 → 30/04/23
研究計畫: Other Government Ministry Institute
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無線式可擴增之神經感測與刺激微系統技術平台開發- 多通道多相位刺激器電路設計
Ker, M.-D. (PI)
1/08/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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智慧型可適性深腦刺激系統於帕金森氏症精準治療之研究-智慧型可適性深腦刺激系統於帕金森氏症精準治療之研究(1/2)
Ker, M.-D. (PI)
1/01/21 → 31/12/21
研究計畫: Other Government Ministry Institute
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A Versatile 8-Channel High Voltage Stimulator for Comprehensive Neural Stimulation
Lin, K. T. & Ker, M. D., 2024, ISCAS 2024 - IEEE International Symposium on Circuits and Systems. Institute of Electrical and Electronics Engineers Inc., (Proceedings - IEEE International Symposium on Circuits and Systems).研究成果: Conference contribution › 同行評審
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Cost-Efficient Solution to Overcome Latch-Up Path in 5 V-Tolerant I/O With Low-Voltage Biased NBL Isolation Ring in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD Technology
Hsu, C. W. & Ker, M. D., 2024, (Accepted/In press) 於: IEEE Transactions on Electron Devices. p. 1-4 4 p.研究成果: Article › 同行評審
1 引文 斯高帕斯(Scopus) -
Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications
Wu, C. Y., Huang, C. W., Chen, Y. W., Lai, C. K., Hung, C. C. & Ker, M. D., 1 6月 2024, 於: IEEE Transactions on Biomedical Circuits and Systems. 18, 3, p. 539-551 13 p.研究成果: Article › 同行評審
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Embedded Deep-Nwell Collector Used to Improve Latch-Up Immunity of Multi-Functional I/O Buffer with Indirect Power-Connected N-Well
Hsu, C. W., Ker, M. D., Chung, P. L., Cheng, C. T. & Chen, C. P., 2024, 2024 IEEE International Reliability Physics Symposium, IRPS 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (IEEE International Reliability Physics Symposium Proceedings).研究成果: Conference contribution › 同行評審
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Investigation of Latch-Up Immunity in 0.18-f.1M BCD Process with Deep Trench Isolation
Ho, W. Y., Ker, M. D., Wang, C. C., Chiang, T. Y. & Wei, I. J., 2024, 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings).研究成果: Conference contribution › 同行評審
獎項
活動
- 2 Editorial work
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IEEE Transactions on Biomedical Circuits and Systems (事件)
Ker, M.-D. (Member of editorial board)
1 1月 2018 → 31 12月 2019活動: Editorial work
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IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY (事件)
Ker, M.-D. (Member of editorial board)
1 6月 2012 → 31 5月 2021活動: Editorial work