每年研究成果
每年研究成果
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搜尋結果
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2022
On Reducing LDE Variations in Modern Analog Placement
AK, T., Patyal, A., Chi, H. Y., Lin, P. H. & Chen, H. M., 2022, (Accepted/In press) 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. p. 1 1 p.研究成果: Article › 同行評審
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Pole-aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire-Crossings
Patyal, A., Chen, H. M., Lin, P-H., Fang, G. Q. & Chen, S. Y. H., 2022, (Accepted/In press) 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. p. 1 1 p.研究成果: Article › 同行評審
1 引文 斯高帕斯（Scopus） -
2020
Corner-Stitching-Based Multilayer Obstacle-Avoiding Component-to-Component Rectilinear Minimum Spanning Tree Construction
Su, Y. Y., Wang, S. H., Wu, W. L. & Lin, M. P. H., 3月 2020, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39, 3, p. 675-685 11 p., 8599013.研究成果: Article › 同行評審
1 引文 斯高帕斯（Scopus） -
2018
SAT-Based fault equivalence checking in functional safety verification
Dao, A. Q., Lin, P-H. & Mishchenko, A., 1 12月 2018, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37, 12, p. 3198-3205 8 p., 8252779.研究成果: Article › 同行評審
2 引文 斯高帕斯（Scopus） -
2017
An efficient two-phase ILP-based algorithm for precise CMOS RFIC layout generation
Tseng, T. M., Li, B., Yeh, C. F., Jhan, H. C., Tsai, Z-M., Lin, P-H. & Schlichtmann, U., 1 8月 2017, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 8, p. 1313-1326 14 p., 7745860.研究成果: Article › 同行評審
1 引文 斯高帕斯（Scopus） -
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters
Chou, P. Y., Chen, N. C., Lin, P-H. & Graeb, H., 1 8月 2017, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25, 8, p. 2234-2247 14 p., 7896631.研究成果: Article › 同行評審
6 引文 斯高帕斯（Scopus） -
Minimizing detection-to-boosting latency toward low-power error-resilient circuits
Hsu, C. C., Hashimoto, M. & Lin, P-H., 1 6月 2017, 於: Integration, the VLSI Journal. 58, p. 236-244 9 p.研究成果: Article › 同行評審
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Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing
Lin, P-H., Hsiao, V. W. H., Lin, C. Y. & Chen, N. C., 1 8月 2017, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36, 8, p. 1274-1286 13 p., 7883919.研究成果: Article › 同行評審
14 引文 斯高帕斯（Scopus） -
2016
DeMixGen: Deterministic mixed-signal layout generation with separated analog and digital signal paths
Lin, P-H., Chang, P. H., Lee, S. Y. & Graeb, H. E., 1 8月 2016, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 35, 8, p. 1229-1242 14 p., 7347380.研究成果: Article › 同行評審
4 引文 斯高帕斯（Scopus） -
Parasitic-aware common-centroid FinFET placement and routing for current-ratio matching
Wu, P. H., Lin, P-H., Li, X. & Ho, T. Y., 1 4月 2016, 於: ACM Transactions on Design Automation of Electronic Systems. 21, 3, 39.研究成果: Article › 同行評審
4 引文 斯高帕斯（Scopus） -
2015
A novel analog physical synthesis methodology integrating existent design expertise
Wu, P. H., Lin, P-H., Chen, T. C., Yeh, C. F., Li, X. & Ho, T. Y., 1 2月 2015, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34, 2, p. 199-212 14 p., 6981934.研究成果: Article › 同行評審
37 引文 斯高帕斯（Scopus） -
Clock-tree aware multibit flip-flop generation during placement for power optimization
Lin, P-H., Hsu, C. C. & Chen, Y. C., 1 2月 2015, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 34, 2, p. 280-292 13 p., 6975058.研究成果: Article › 同行評審
23 引文 斯高帕斯（Scopus） -
Crosstalk-aware multi-bit flip-flop generation for power optimization
Hsu, C. C., Lin, P-H. & Chang, Y. T., 1 1月 2015, 於: Integration, the VLSI Journal. 48, 1, p. 146-157 12 p.研究成果: Article › 同行評審
4 引文 斯高帕斯（Scopus） -
2014
Exploring feasibilities of symmetry islands and monotonic current paths in slicing trees for analog placement
Wu, P. H., Lin, P-H., Chen, T. C., Yeh, C. F., Ho, T. Y. & Liu, B. D., 1 1月 2014, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33, 6, p. 879-892 14 p., 6816125.研究成果: Article › 同行評審
22 引文 斯高帕斯（Scopus） -
2013
1-D cell generation with printability enhancement
Wu, P. H., Lin, P-H., Chen, T. C., Ho, T. Y., Chen, Y. C., Siao, S. R. & Lin, S. H., 11 3月 2013, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 3, p. 419-432 14 p., 6461981.研究成果: Article › 同行評審
9 引文 斯高帕斯（Scopus） -
Common-centroid capacitor layout generation considering device matching and parasitic minimization
Lin, P-H., He, Y. T., Hsiao, V. W. H., Chang, R. G. & Lee, S. Y., 15 7月 2013, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32, 7, p. 991-1002 12 p., 6532364.研究成果: Article › 同行評審
36 引文 斯高帕斯（Scopus） -
2011
Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist
Lee, S. Y., Chen, C. Y., Hong, J. H., Chang, R. G. & Lin, P-H., 1 2月 2011, 於: Microelectronics Journal. 42, 2, p. 347-357 11 p.研究成果: Article › 同行評審
10 引文 斯高帕斯（Scopus） -
Post-placement power optimization with multi-bit flip-flops
Lin, P-H., Hsu, C. C. & Chang, Y. T., 1 12月 2011, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 12, p. 1870-1882 13 p., 6071086.研究成果: Article › 同行評審
13 引文 斯高帕斯（Scopus） -
Thermal-driven analog placement considering device matching
Lin, P-H., Zhang, H., Wong, M. D. F. & Chang, Y. W., 1 3月 2011, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30, 3, p. 325-336 12 p., 5715604.研究成果: Article › 同行評審
26 引文 斯高帕斯（Scopus） -
2009
Analog placement based on symmetry-Island formulation
Lin, P-H., Chang, Y. W. & Lin, S. C., 1 6月 2009, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28, 6, p. 791-804 14 p., 4957593.研究成果: Article › 同行評審
70 引文 斯高帕斯（Scopus）