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查看斯高帕斯 (Scopus) 概要
林 柏宏
教授
前瞻半導體研究所
h-index
h10-index
h5-index
927
引文
19
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
379
引文
11
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
58
引文
4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2007
2024
每年研究成果
概覽
指紋
網路
計畫
(13)
研究成果
(71)
類似的個人檔案
(6)
指紋
查看啟用 Mark Po-Hung Lin 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
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Keyphrases
Analog Circuits
19%
Analog Design
11%
Analog Layout
16%
Analog Layout Synthesis
17%
Analog Placement
45%
Analog Signal
11%
B+ Tree
13%
Binary Weights
13%
CAD Contest
9%
Capacitor Array
13%
Capacitors
20%
Cell Generation
10%
Charge Scaling
8%
Chip Area
10%
Circuit Netlist
8%
Circuit Performance
22%
Clock Network
7%
Clock Tree
11%
Common Centroid
26%
Common-centroid Layout
7%
Crosstalk-aware
6%
Current Path
6%
Design Skills
6%
Devices Matching
10%
Fin Field-effect Transistor (FinFET)
6%
Flip-flop
11%
Late-breaking Results
10%
Layout Design
26%
Layout Generation
24%
Low Power
16%
Mixed-signal Circuits
7%
Mixed-signal Design
8%
MOM Capacitor
6%
Multi-bit
7%
Multi-bit Flip-flop
27%
Parasitic Capacitance
7%
Power Consumption
10%
Power Optimization
24%
Printability
6%
Problem Formulation
7%
Process Technology
9%
Result-oriented
8%
Retention Register
6%
SAR ADC
11%
Signaling Pathway
8%
Slicing Tree
6%
System-on-chip Design
8%
Thermal Driving
6%
Thermal Profile
8%
Wirelength
9%
Computer Science
Analog Circuit
29%
Analog-to-Digital Converter
10%
Approximation (Algorithm)
10%
Building-Blocks
5%
Close Proximity
6%
Combinational Logic
8%
Computer Aided Design
13%
Data Converter
5%
Design Automation
6%
Digital-to-Analog Converter
10%
Effective Approach
5%
Electronic Design Automation
10%
Experimental Result
100%
Floorplan Representation
5%
Floorplanning
6%
Integer-Linear Programming
12%
Integrated Circuit
13%
Integrated Circuit Design
7%
Low Power Consumption
5%
Monitoring System
5%
Parasitic Capacitance
10%
Performance Degradation
12%
Physical Design
5%
Placement Algorithm
10%
Power Consumption
24%
Power Optimization
20%
Presented Approach
6%
Problem Formulation
18%
Reinforcement Learning
6%
Routing Topology
10%
Search Space
9%
Simulated Annealing
6%
Solution Quality
10%
System-on-Chip
20%
Technology Advance
10%
Thermal Gradient
6%
Thermal Profile
9%
Threshold Voltage
6%
Time Complexity
6%
Engineering
Analog Circuit
21%
Analog Design
13%
Analog Integrated Circuits
6%
Analog-to-Digital Converter
6%
Building Block
8%
Chip Area
13%
Circuit Performance
33%
Critical Path
5%
Crosstalk
7%
Current Drain
5%
Current Flow
6%
Design Process
5%
Design Style
5%
Design Time
10%
Digital-to-Analog Converter
8%
Electric Power Utilization
12%
Engineering
6%
Experimental Result
57%
Feature Size
5%
Flip Flop Circuits
20%
Internet-Of-Things
6%
Learning System
5%
Linear Programming
12%
Low Power Consumption
5%
Metal Layer
5%
Millimeter Wave
6%
Nanometre
5%
Nodes
10%
Parasitic Capacitance
9%
Performance Degradation
6%
Placement Constraint
6%
Problem Formulation
5%
Reinforcement Learning
6%
Search Space
5%
Signal Path
11%
Storage Size
5%
Subcircuit
6%
Successive Approximation
6%
System-on-Chip
16%
Thermal Effect
5%
Thermal Gradient
8%
