跳至主導覽
跳至搜尋
跳過主要內容
國立陽明交通大學研發優勢分析平台 首頁
English
中文
首頁
人員
單位
研究成果
計畫
獎項
活動
貴重儀器
影響
按專業知識、姓名或所屬機構搜尋
查看斯高帕斯 (Scopus) 概要
林 柏宏
教授
前瞻半導體研究所
h-index
h10-index
h5-index
904
引文
19
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
362
引文
10
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
52
引文
4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
2007
2024
每年研究成果
概覽
指紋
網路
計畫
(13)
研究成果
(71)
類似的個人檔案
(6)
指紋
查看啟用 Mark Po-Hung Lin 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Analog Placement
42%
Multi-bit Flip-flop
27%
Layout Design
26%
Common Centroid
26%
Layout Generation
24%
Power Optimization
24%
Circuit Performance
22%
Capacitors
20%
Analog Circuits
17%
Analog Layout Synthesis
17%
Low Power
16%
Analog Layout
16%
B+ Tree
13%
Binary Weights
13%
Capacitor Array
13%
Flip-flop
11%
Analog Design
11%
Clock Tree
11%
Analog Signal
11%
SAR ADC
11%
Devices Matching
10%
Cell Generation
10%
Late-breaking Results
10%
Power Consumption
10%
CAD Contest
9%
Process Technology
9%
Chip Area
9%
Signaling Pathway
8%
Mixed-signal Design
8%
System-on-chip Design
8%
Result-oriented
8%
Wirelength
8%
Charge Scaling
8%
Thermal Profile
8%
Circuit Netlist
8%
Mixed-signal Circuits
7%
Parasitic Capacitance
7%
Common-centroid Layout
7%
Multi-bit
7%
Problem Formulation
7%
Clock Network
7%
Design Skills
6%
Slicing Tree
6%
Crosstalk-aware
6%
Current Path
6%
MOM Capacitor
6%
Thermal Driving
6%
Printability
6%
Retention Register
6%
Fin Field-effect Transistor (FinFET)
6%
Computer Science
Experimental Result
100%
Analog Circuit
29%
Power Consumption
24%
Power Optimization
20%
Problem Formulation
18%
System-on-Chip
17%
Computer Aided Design
13%
Integrated Circuits
13%
Integer-Linear Programming
12%
Performance Degradation
12%
Technology Advance
10%
Digital-to-Analog Converter
10%
Parasitic Capacitance
10%
Analog-to-Digital Converter
10%
Electronic Design Automation
10%
Approximation (Algorithm)
10%
Routing Topology
10%
Solution Quality
10%
Placement Algorithm
10%
Thermal Profile
9%
Search Space
9%
Combinational Logic
8%
Integrated Circuit Design
7%
Floorplanning
6%
Close Proximity
6%
Presented Approach
6%
Time Complexity
6%
Design Automation
6%
Simulated Annealing
6%
Reinforcement Learning
6%
Thermal Gradient
6%
Threshold Voltage
6%
Floorplan Representation
5%
Physical Design
5%
Low Power Consumption
5%
Monitoring System
5%
Data Converter
5%
Effective Approach
5%
Building-Blocks
5%
Engineering
Experimental Result
58%
Circuit Performance
33%
Analog Circuit
24%
Flip Flop Circuits
20%
System-on-Chip
16%
Tasks
15%
Chip Area
13%
Analog Design
13%
Linear Programming
13%
Electric Power Utilization
12%
Signal Path
11%
Parasitic Capacitance
10%
Design Time
10%
Nodes
10%
Digital-to-Analog Converter
8%
Thermal Gradient
8%
Building Block
8%
Crosstalk
7%
Successive Approximation
6%
Current Flow
6%
Subcircuit
6%
Analog-to-Digital Converter
6%
Engineering
6%
Millimeter Wave
6%
Internet of Things
6%
Reinforcement Learning
6%
Performance Degradation
6%
Placement Constraint
6%
Analog Integrated Circuits
6%
Design Style
5%
Problem Formulation
5%
Critical Path
5%
Thermal Effect
5%
Search Space
5%
Storage Size
5%
Nanometre
5%
Low Power Consumption
5%
Metal Layer
5%
Current Drain
5%
Feature Size
5%
Data Converter
5%
Design Process
5%
