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查看斯高帕斯 (Scopus) 概要
趙 家佐
教授
電子研究所
h-index
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h5-index
575
引文
14
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
217
引文
9
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
88
引文
4
h-指數
按照存儲在普爾（Pure）的出版物數量及斯高帕斯（Scopus）引文計算。
1999
2024
每年研究成果
概覽
指紋
網路
計畫
(30)
研究成果
(85)
類似的個人檔案
(3)
指紋
查看啟用 Mango Chia-Tso Chao 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
排序方式
重量
按字母排序
Keyphrases
Array-based
15%
Bridging Faults
13%
Cell-Aware Test
26%
Cell-based
17%
Clustering Methods
11%
CMOS Design
16%
Compactor
24%
Convolutional Neural Network
27%
Defect Pattern
15%
Defective Parts
15%
Design Flow
15%
EDRAM
17%
Fault Model
44%
Fault Test
13%
Faulty Behavior
12%
Fitting Method
12%
Global Routing
15%
Industrial Design
16%
IR Drop
39%
Local Processes
13%
Machine Learning Techniques
19%
MetaFormer
13%
Model Fitting
18%
Monte Carlo Tree Search
11%
Multi-threshold CMOS (MTCMOS)
27%
Neural Network
29%
Novel Object Recognition
18%
Observation Window
15%
Obstacle Avoidance
15%
Parts per Million
26%
Pattern Information
18%
Power Distribution Network
26%
Power Switch
23%
Process Technology
19%
Process Variation
29%
Rectilinear Steiner Tree
15%
Result-oriented
18%
Return Materials Authorization
15%
Ring Oscillator
11%
Router
19%
SRAM Design
16%
Subthreshold SRAM
21%
System Testing
14%
Test Escape
12%
Test Quality
14%
Testing Method
57%
Timing Optimization
14%
Training Time
11%
Wafer
24%
Wafer Patterns
11%
Computer Science
Analytical Model
10%
Arbitrary Size
10%
Buffer Insertion
10%
Case Study
7%
Convolutional Neural Network
26%
Criticality
10%
de-noising
10%
Design Complexity
10%
Design Procedure
7%
Design Technique
11%
Domain Circuit
7%
Electronic Design Automation
10%
Experimental Result
100%
Fault Coverage
15%
Field Programmable Gate Arrays
15%
Global Routing
15%
Information Pattern
13%
Integrated Circuit
8%
Learning Framework
7%
Learning System
15%
Machine Learning
15%
Machine Learning Technique
18%
Manhattan Distance
7%
Memory Design
7%
Neural Network
23%
Observation Window
15%
Physical Design
8%
Power Consumption
16%
Power Distribution Network
26%
Prediction Model
12%
Process Variation
25%
Product Design
28%
Random Decision Forest
10%
Reinforcement Learning
10%
Research Effort
21%
Research Topic
7%
Routing Congestion
10%
Scan Chain
10%
Speed-up
11%
Supply Voltage
16%
Test Algorithm
25%
Test Data Volume
10%
Threshold Voltage
7%
Timing Analysis
14%
Timing Constraint
7%
Timing Optimization
14%
Training Dataset
7%
Training Sample
11%
Transition Signal
15%
Tree Search
12%
Engineering
Artificial Neural Network
10%
Binary Search
7%
Boolean Operation
6%
Cell Design
7%
Cell Pair
7%
Chip Process
5%
Compactor
21%
Convolutional Neural Network
15%
Core Model
6%
Critical Path
10%
Design Change
10%
Design Flow
15%
Design Parameter
5%
Design Technique
6%
Electric Power Distribution
15%
Electric Power Utilization
7%
Electromigration
7%
Electronic Design Automation
10%
Estimation Scheme
10%
Experimental Result
52%
Fault Model
48%
Field Programmable Gate Arrays
15%
Fits and Tolerances
11%
Frame Time
15%
Functional Test
5%
Gate Oxide
10%
Machine Learning Technique
15%
Metrics
11%
Nodes
13%
Observables
12%
Operating Mode
5%
Optimal Placement
5%
Oscillator
11%
Power Distribution
15%
Process Variation
28%
Product Design
23%
Quality Control
5%
Random Access Memory
10%
Random Forest
7%
Schematic Diagram
5%
Spatial Correlation
6%
SPICE
15%
Supply Voltage
5%
Test Method
32%
Test Structure
30%
Test Time
27%
Testing Method
10%
Thin-Film Transistor
10%
Total Profit
10%
VLSI Circuits
5%
