每年專案
個人檔案
研究專長
積體電路測試、電子設計自動化、積體電路統計時序分析
經歷
2006/08~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, University of California, Santa Barbara
外部位置
指紋
查看啟用 Mango Chia-Tso Chao 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
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網路
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
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Improving Cell-Aware Test for Intra-Cell Short Defects
Lee, D. Z., Chen, Y. Y., Wu, K. C. & Chao, M. C. T., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 436-441 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).研究成果: Conference contribution › 同行評審
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Rule Generation for Classifying SLT Failed Parts
Hsu, H. C., Lu, C. C., Wang, S. W., Jones, K., Wu, K. C. & Chao, M. C. T., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; 卷 2022-April).研究成果: Conference contribution › 同行評審
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Test Methodology for Defect-Based Bridge Faults
Chang, S. W., Nien, Y. T., Hu, Y. P., Wu, K. C., Wang, C. C., Huang, F. S., Tang, Y. L., Chen, Y. C., Chen, M. C. & Chao, M. C. T., 2022, (Accepted/In press) 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems.研究成果: Article › 同行評審
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Identifying good-dice-in-bad-neighborhoods using artificial neural networks
Yang, C. H., Yen, C. H., Wang, T. R., Chen, C. T., Chern, M., Chen, Y. Y., Lee, J. N., Kao, S. Y., Wu, K-C. & Chao, C-T., 25 4月 2021, Proceedings - 2021 IEEE 39th VLSI Test Symposium, VTS 2021. IEEE Computer Society, 9441055. (Proceedings of the IEEE VLSI Test Symposium; 卷 2021-April).研究成果: Conference contribution › 同行評審
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Methodology of Generating Timing-Slack-Based Cell-Aware Tests
Nien, Y. T., Wu, K. C., Lee, D. Z., Chen, Y. Y., Chen, P. L., Chern, M., Lee, J. N., Kao, S. Y. & Chao, M. C. T., 2021, (Accepted/In press) 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.研究成果: Article › 同行評審