Lan-Da Van

2024

Accurate Mental Stress Detection Using Sequential Backward Selection and Adaptive Synthetic Methods

Tseng, H. C., Tai, K. Y., Ma, Y. Z., Van, L. D., Ko, L. W. & Jung, T. P., 2024, 於: IEEE Transactions on Neural Systems and Rehabilitation Engineering. 32, p. 3095-3103 9 p.

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2 引文斯高帕斯（Scopus）

2022

Person Tracking by Fusing Posture Data from UAV Video and Wearable Sensors

Mukashev, A., Van, L. D., Sharma, S., Tandia, M. F. & Tseng, Y. C., 15 12月 2022, 於: IEEE Sensors Journal. 22, 24, p. 24150-24160 11 p.

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5 引文斯高帕斯（Scopus）

2021

Hardware-Oriented Memory-Limited Online Artifact Subspace Reconstruction (HMO-ASR) Algorithm

Van, L. D., Tu, Y. C., Chang, C. Y., Wang, H. J. & Jung, T. P., 1 12月 2021, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 68, 12, p. 3493-3497 5 p.

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5 引文斯高帕斯（Scopus）

Things in the air: tagging wearable IoT information on drone videos

Van, L. D., Zhang, L. Y., Chang, C. H., Tong, K. L., Wu, K. R. & Tseng, Y. C., 12月 2021, 於: Discover Internet of Things. 1, 1, 6.

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19 引文斯高帕斯（Scopus）

2020

An Intelligent Elevator Development and Management System

Van, L.-D., Lin, Y.-B., Wu, T. H. & Lin, Y.-C., 6月 2020, 於: IEEE Systems Journal. 14, 2, p. 3015-3026 12 p., 8743399.

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16 引文斯高帕斯（Scopus）

Green Elevator Scheduling Based on IoT Communications

Van, L.-D., Lin, Y.-B., Wu, T. H. & Chao, T.-H., 20 2月 2020, 於: IEEE Access. 8, p. 38404-38415 12 p., 9005228.

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9 引文斯高帕斯（Scopus）

2019

Planttalk: A smartphone-based intelligent hydroponic plant box

Van, L.-D., Lin, Y.-B., Wu, T. H., Lin, Y.-W., Peng, S. R., Kao, L. H. & Chang, C. H., 2 4月 2019, 於: Sensors (Switzerland). 19, 8, 1763.

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22 引文斯高帕斯（Scopus）

Symmetry Incorporated Cost-Effective Architectures for Two-Dimensional Digital Filters

Van, L.-D., Khoo, I. H., Chen, P. Y. & Reddy, H. H. C., 1 1月 2019, 於: IEEE Circuits and Systems Magazine. 19, 1, p. 33-54 22 p., 8640217.

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11 引文斯高帕斯（Scopus）

2018

Efficient Progressive Radiance Estimation Engine Architecture and Implementation for Progressive Photon Mapping

Chiu, C. C., Van, L.-D. & Lin, Y. S., 8月 2018, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 65, 8, p. 2491-2502 12 p.

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1 引文斯高帕斯（Scopus）

2016

Cost-Effective and Variable-Channel FastICA Hardware Architecture and Implementation for EEG Signal Processing

Van, L.-D., Huang, P. Y. & Lu, T. C., 1 1月 2016, 於: Journal of Signal Processing Systems. 82, 1, p. 91-113 23 p.

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13 引文斯高帕斯（Scopus）

2014

General formulation of shift and delta operator based 2-D VLSI filter structures without global broadcast and incorporation of the symmetry

Khoo, I. H., Reddy, H. C., Van, L.-D. & Lin, C. T., 10月 2014, 於: Multidimensional Systems and Signal Processing. 25, 4, p. 795-828 34 p.

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8 引文斯高帕斯（Scopus）

2012

An improved noc design methodology using latency-guarantee network architecture and communication-contention-aware cost function

Lin, L. Y., Wang, C. Y. & Van, L.-D., 8月 2012, 於: International Journal of Electrical Engineering. 19, 4, p. 179-190 12 p.

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2011

A power-area efficient geometry engine with low-complexity subdivision algorithm for 3-d graphics system

Van, L.-D. & Sheu, T. Y., 7 4月 2011, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 58, 9, p. 2211-2224 14 p., 5741869.

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1 引文斯高帕斯（Scopus）

Efficient detection algorithms for MIMO communication systems

Wu, D. Y. & Van, L.-D., 3月 2011, 於: Journal of Signal Processing Systems. 62, 3, p. 427-442 16 p.

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1 引文斯高帕斯（Scopus）

Energy-efficient FastICA implementation for biomedical signal separation

Van, L.-D., Wu, D. Y. & Chen, C. S., 1 11月 2011, 於: IEEE Transactions on Neural Networks. 22, 11, p. 1809-1822 14 p., 6032107.

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59 引文斯高帕斯（Scopus）

Power-efficient and cost-effective 2-D symmetry filter architectures

Chen, P. Y., Van, L.-D., Khoo, I. H., Reddy, H. C. & Lin, C. T., 2011, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 58, 1, p. 112-125 14 p., 5549959.

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30 引文斯高帕斯（Scopus）

2009

Power-efficient pipelined reconfigurable fixed-width Baugh-Wooley multipliers

Tu, J. H. & Van, L.-D., 1 10月 2009, 於: IEEE Transactions on Computers. 58, 10, p. 1346-1355 10 p.

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53 引文斯高帕斯（Scopus）

2008

Cost-effective triple-mode reconfigurable pipeline FFT/IFFT/2-D DCT processor

Lin, C.-T., Yu, Y. C. & Van, L.-D., 1 8月 2008, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 16, 8, p. 1058-1071 14 p., 4570474.

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28 引文斯高帕斯（Scopus）

2007

Adaptive low-error fixed-width Booth multipliers

Song, M. A., Van, L.-D. & Kuo, S. Y., 6月 2007, 於: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E90-A, 6, p. 1180-1187 8 p.

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42 引文斯高帕斯（Scopus）

VLSI architecture for the low-computation cycle and power-efficient recursive DFT/IDFT design

Van, L.-D., Lin, C. T. & Yu, Y. C., 8月 2007, 於: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. E90-A, 8, p. 1644-1652 9 p.

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15 引文斯高帕斯（Scopus）

2005

Generalized low-error area-efficient fixed-width multipliers

Van, L.-D. & Yang, C. C., 1 8月 2005, 於: IEEE Transactions on Circuits and Systems I: Regular Papers. 52, 8, p. 1608-1619 12 p.

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96 引文斯高帕斯（Scopus）

2002

A generalized methodology for lower-error area-efficient fixed-width multipliers

Van, L.-D. & Lee, S. H., 1 1月 2002, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 65-68 4 p.

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6 引文斯高帕斯（Scopus）

A new 2-D systolic digital filter architecture without global broadcast

Van, L.-D., 8月 2002, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 10, 4, p. 477-486 10 p.

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28 引文斯高帕斯（Scopus）

Pipelined RLS adaptive architecture using relaxed givens rotations (RGR)

Van, L.-D. & Chang, C. H., 2002, 於: Proceedings - IEEE International Symposium on Circuits and Systems. 1, p. 37-40 4 p.

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2 引文斯高帕斯（Scopus）

2001

An efficient systolic architecture for the DLMS adaptive filter and its applications

Van, L.-D. & Feng, W. S., 4月 2001, 於: IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing. 48, 4, p. 359-366 8 p.

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64 引文斯高帕斯（Scopus）

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