每年研究成果
每年研究成果
- 20結果
搜尋結果
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2015
SUBMICRON CONNECTION LAYER AND METHOD FOR USING THE SAME TO CONNECT WAFERS
Chen, K.-N. (Inventor), 10 2月 2015, 專利號 US 8,951,837 B2研究成果: Patent
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2014
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HETEROSTRUCTURE CONTAINING IC AND LED AND METHOD FOR FABRICATING THE SAME
Chen, K.-N. (Inventor), 25 3月 2014, 專利號 US 8,679,891 B2研究成果: Patent
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INTEGRATED CIRCUIT DEVICE
Chen, K.-N. (Inventor) & Chen, H.-M. (Inventor), 18 2月 2014, 專利號 US 8,653,641 B2研究成果: Patent
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THREE-DIMENSIONAL INTEGRATED CIRCUIT
Chen, K.-N. (Inventor) & Chen, H.-M. (Inventor), 18 11月 2014, 專利號 US 8,890,303 B2研究成果: Patent
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2013
BONDING METHOD FOR THREE-DIMENSIONAL INTEGRATED CIRCUIT AND THREE-DIMENSIONAL INTEGRATED CIRCUIT THEREOF
Chen, K.-N. (Inventor), 13 8月 2013, 專利號 US 8,508,041 B2研究成果: Patent
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ELECTRICAL TEST STRUCTURE APPLYING 3D-ICS BONDING TECHNOLOGY FOR STACKING ERROR MEASUREMENT
Chen, K.-N. (Inventor), 1 10月 2013, 專利號 US 8,546,952 B2研究成果: Patent
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ESD PROTECTION STRUCTURE FOR 3D IC
Chen, K.-N. (Inventor) & Chen, H.-M. (Inventor), 24 1月 2013, 專利號 10-1227872研究成果: Patent
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HETEROSTRUCTURE CONTAINING IC AND LED AND METHOD FOR FABRICATING THE SAME
Chen, K.-N. (Inventor), 17 9月 2013, 專利號 US 8,536,613 B2研究成果: Patent
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三維積體電路的靜電放電防護結構
Chen, H.-M. (Inventor) & Chen, K.-N. (Inventor), 21 11月 2013, 專利號 I416706研究成果: Patent
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