每年專案
個人檔案
研究專長
AI運算平台設計、近似計算於AI之應用、安全與硬體特洛伊、SoC設計自動化
經歷
1.Software Engineer, Design Technology Solutions, Intel Corporation, 08/2011 – 07/2013
2.Research Assistant, Energy Aware Computing (EnyAC) Group, Carnegie Mellon University, 08/2006 – 07/2011
教育/學術資格
PhD, 資訊工程, Carnegie Mellon University
外部位置
指紋
查看啟用 Kai-Chiang Wu 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 1 類似的個人檔案
網路
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
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Transformer 類神經網路之軟硬體整合加速方案-總計畫暨子計畫一：考量硬體特性與模型量化之 Transformer 類神經網路架構搜尋技術
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-總計畫暨子計畫一：考量硬體特性與模型量化之 Transformer 類神經網路架構搜尋技術
1/08/24 → 31/07/25
研究計畫: Other Government Ministry Institute
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Transformer 類神經網路之軟硬體整合加速方案-總計畫暨子計畫一：考量硬體特性與模型量化之 Transformer 類神經網路架構搜尋技術
1/08/23 → 31/07/24
研究計畫: Other Government Ministry Institute
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智慧終端系統晶片研發與新創事業計畫-子計畫二：以終端系統為考量之視覺深度神經網路模組設計(2/2)
1/05/21 → 31/07/22
研究計畫: Other Government Ministry Institute
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智慧終端系統晶片研發與新創事業計畫-子計畫二：以終端系統為考量之視覺深度神經網路模組設計(1/2)
1/05/20 → 30/04/21
研究計畫: Other Government Ministry Institute
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CNN-Based Stochastic Regression for IDDQ Outlier Identification
Yen, C. H., Chen, C. T., Wen, C. Y., Chen, Y. Y., Lee, J. N., Kao, S. Y., Wu, K. C. & Chao, C-T., 2023, (Accepted/In press) 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. p. 1 1 p.研究成果: Article › 同行評審
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Improving Cell-Aware Test for Intra-Cell Short Defects
Lee, D. Z., Chen, Y. Y., Wu, K. C. & Chao, M. C. T., 2022, Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022. Bolchini, C., Verbauwhede, I. & Vatajelu, I. (編輯). Institute of Electrical and Electronics Engineers Inc., p. 436-441 6 p. (Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022).研究成果: Conference contribution › 同行評審
2 引文 斯高帕斯（Scopus） -
Rule Generation for Classifying SLT Failed Parts
Hsu, H. C., Lu, C. C., Wang, S. W., Jones, K., Wu, K. C. & Chao, M. C. T., 2022, Proceedings - 2022 IEEE 40th VLSI Test Symposium, VTS 2022. IEEE Computer Society, (Proceedings of the IEEE VLSI Test Symposium; 卷 2022-April).研究成果: Conference contribution › 同行評審
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Test Methodology for Defect-Based Bridge Faults
Chang, S. W., Nien, Y. T., Hu, Y. P., Wu, K. C., Wang, C. C., Huang, F. S., Tang, Y. L., Chen, Y. C., Chen, M. C. & Chao, M. C. T., 2022, (Accepted/In press) 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems.研究成果: Article › 同行評審
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Timing Variability-Aware Analysis and Optimization for Variable-Latency Designs
Huang, N. C., Cheng, C. W. & Wu, K. C., 1 1月 2022, 於: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30, 1, p. 81-94 14 p.研究成果: Article › 同行評審
1 引文 斯高帕斯（Scopus）