Jyh-Chyurn Guo

2022

Layout Optimization and Parasitic Reduction in Sub-60-nm nMOSFETs for Super-350-GHz f_MAX

Guo, J. C. & Ou, J. R., 1 7月 2022, 於: IEEE Transactions on Electron Devices. 69, 7, p. 3589-3595 7 p.

研究成果: Article › 同行評審

2020

SiC Strained nMOSFETs with Enhanced High- Frequency Performance and Impact on Flicker Noise and Random Telegraph Noise

Guo, J-C. & Chang, C. S., 6月 2020, 於: IEEE Transactions on Microwave Theory and Techniques. 68, 6, p. 2259-2267 9 p., 9063679.

研究成果: Article › 同行評審

2017

A comprehensive characterization method for lateral profiling of interface traps and trapped charges in P-SONOS cell devices

Guo, J-C. & Du, P. Y., 1 3月 2017, 於: IEEE Transactions on Device and Materials Reliability. 17, 1, p. 121-129 9 p., 7738415.

研究成果: Article › 同行評審

2015

A new method for accurate extraction of source resistance and effective mobility in nanoscale multifinger nMOSFETs

Guo, J-C. & Lo, Y. Z., 1 9月 2015, 於: IEEE Transactions on Electron Devices. 62, 9, p. 3004-3011 8 p., 7181674.

研究成果: Article › 同行評審

9 引文斯高帕斯（Scopus）

2013

Narrow-width effect on high-frequency performance and RF noise of sub-40-nm multifinger nMOSFETs and pMOSFETs

Yeh, K. L. & Guo, J-C., 7 1月 2013, 於: IEEE Transactions on Electron Devices. 60, 1, p. 109-116 8 p., 6381483.

研究成果: Article › 同行評審

28 引文斯高帕斯（Scopus）

2011

A new method for layout-dependent parasitic capacitance analysis and effective mobility extraction in nanoscale multifinger MOSFETs

Yeh, K. L. & Guo, J-C., 1 9月 2011, 於: IEEE Transactions on Electron Devices. 58, 9, p. 2838-2846 9 p., 5960782.

研究成果: Article › 同行評審

19 引文斯高帕斯（Scopus）

Layout-dependent stress effect on high-frequency characteristics and flicker noise in multifinger and donut MOSFETs

Yeh, K. L. & Guo, J-C., 1 9月 2011, 於: IEEE Transactions on Electron Devices. 58, 9, p. 3140-3146 7 p., 5944963.

研究成果: Article › 同行評審

7 引文斯高帕斯（Scopus）

2010

The impact of layout-dependent STI stress and effective width on low-frequency noise and high-frequency performance in nanoscale nMOSFETs

Yeh, K. L. & Guo, J-C., 1 11月 2010, 於: IEEE Transactions on Electron Devices. 57, 11, p. 3092-3100 9 p., 5594629.

研究成果: Article › 同行評審

10 引文斯高帕斯（Scopus）

The impact of uni-axial strain on low frequency noise in nanoscale p-Channel metal-oxide-semiconductor field effect transistors under dynamic body biases

Yeh, K. L., Ku, C. Y. & Guo, J-C., 1 8月 2010, 於: Japanese Journal of Applied Physics. 49, 8 PART 1, 084201.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

2009

A broadband and scalable lossy substrate model for RF noise simulation and analysis in nanoscale MOSFETs with various pad structures

Guo, J-C. & Tsai, Y. H., 1 2月 2009, 於: IEEE Transactions on Microwave Theory and Techniques. 57, 2, p. 271-281 11 p., 4738427.

研究成果: Article › 同行評審

8 引文斯高帕斯（Scopus）

A new three-dimensional capacitor model for accurate simulation of parasitic capacitances in nanoscale MOSFETs

Guo, J-C. & Yeh, C. T., 26 6月 2009, 於: IEEE Transactions on Electron Devices. 56, 8, p. 1598-1607 10 p.

研究成果: Article › 同行評審

12 引文斯高帕斯（Scopus）

2008

A compact RF CMOS modeling for accurate high-frequency noise simulation in sub-100-nm MOSFETs

Guo, J-C. & Lin, Y. M., 1 9月 2008, 於: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27, 9, p. 1684-1688 5 p., 4603078.

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

A simple analytical model to accurately predict self-resonance frequencies of on-silicon-chip inductors in TEM mode and eddy current mode

Guo, J-C. & Tan, T. Y., 1 8月 2008, 於: Solid-State Electronics. 52, 8, p. 1225-1231 7 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

2007

A broadband and scalable lumped element model for fully symmetric inductors under single-ended and differentially driven operations

Guo, J-C. & Tan, T. Y., 1 8月 2007, 於: IEEE Transactions on Electron Devices. 54, 8, p. 1878-1888 11 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities

Guo, J-C. & Tan, T. Y., 1 11月 2007, 於: IEEE Transactions on Electron Devices. 54, 11, p. 3018-3029 12 p.

研究成果: Article › 同行評審

14 引文斯高帕斯（Scopus）

Halo and LDD engineering for multiple vTH high performance analog CMOS devices

Guo, J-C., 1 8月 2007, 於: IEEE Transactions on Semiconductor Manufacturing. 20, 3, p. 313-321 9 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

2006

A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects

Guo, J-C. & Tan, T. Y., 1 3月 2006, 於: IEEE Transactions on Electron Devices. 53, 3, p. 413-421 9 p.

研究成果: Article › 同行評審

43 引文斯高帕斯（Scopus）

A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling

Guo, J-C. & Lin, Y. M., 1 2月 2006, 於: IEEE Transactions on Electron Devices. 53, 2, p. 339-347 9 p.

研究成果: Article › 同行評審

31 引文斯高帕斯（Scopus）

A new lossy substrate model for accurate RF CMOS noise extraction and simulation with frequency and bias dependence

Guo, J-C. & Lin, Y. M., 1 11月 2006, 於: IEEE Transactions on Microwave Theory and Techniques. 54, 11, p. 3975-3985 11 p., 1717768.

研究成果: Article › 同行評審

6 引文斯高帕斯（Scopus）

Low-K/Cu CMOS-based SoC technology with 115-GHz f_T, 100-GHz f_max, low noise 80-nm RF CMOS, high-Q MiM capacitor, and spiral Cu inductor

Guo, J-C., 1 8月 2006, 於: IEEE Transactions on Semiconductor Manufacturing. 19, 3, p. 331-338 8 p., 1668232.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

2004

0.13-μm low-κ-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel

Guo, J-C., Lien, W. Y., Tsai, T. L., Chen, S. M. & Wu, C. M., 1 5月 2004, 於: IEEE Transactions on Electron Devices. 51, 5, p. 757-763 7 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

0.13-μm RF CMOS and varactors performance optimization by multiple gate layouts

Ho, C. C., Kuo, C. W., Chan, Y. J., Lien, W. Y. & Guo, J-C., 1 12月 2004, 於: IEEE Transactions on Electron Devices. 51, 12, p. 2181-2185 5 p.

研究成果: Article › 同行評審

20 引文斯高帕斯（Scopus）

Pocket implantation effect on drain current flicker noise in analog nMOSFET devices

Wu, J. W., Cheng, C. C., Chiu, K. L., Guo, J-C., Lien, W. Y., Chang, C. S., Huang, G. W. & Wang, T-H., 1 8月 2004, 於: IEEE Transactions on Electron Devices. 51, 8, p. 1262-1266 5 p.

研究成果: Article › 同行評審

28 引文斯高帕斯（Scopus）

2002

Defect detection for short-loop process and SRAM-cell optimization by using Addressable Failure Site Test Structures (AFS-TS)

Doong, K. Y. Y., Hsieh, S., Lin, S. C., Wang, J. R., Shen, B., Hung, L. J., Guo, J-C., Chen, I. C., Young, K. L. & Ching-Hsiang Hsu, C., 1 1月 2002, 於: Proceedings of SPIE-The International Society for Optical Engineering. 4692, p. 81-87 7 p.

研究成果: Article › 同行評審

1998

A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET

Guo, J-C., Liu, Y. C., Chou, M. H., Wang, M. T. & Shone, F., 1 12月 1998, 於: IEEE Transactions on Electron Devices. 45, 7, p. 1518-1523 6 p.

研究成果: Article › 同行評審

22 引文斯高帕斯（Scopus）

1995

Low-temperature hole mobility anomaly in compensated p-channel metal-oxide-semiconductor field-effect transistor

Lu, W. L., Guo, J-C., Kao, C. H., Ching-Hsiang Hsu, C. & Su Lu, L., 7月 1995, 於: Japanese journal of applied physics. 34, 7R, p. 3413-3417 5 p.

研究成果: Article › 同行評審

1 引文斯高帕斯（Scopus）

Transconductance Enhancement due to Back Bias for Submicron NMOSFET

Guo, J-C., Chang, M. C., Lu, C. Y., Chung, S. S. & Hsu, C. C. H., 1 1月 1995, 於: IEEE Transactions on Electron Devices. 42, 2, p. 288-294 7 p.

研究成果: Article › 同行評審

15 引文斯高帕斯（Scopus）

1994

A New Approach to Determine the Effective Channel Length and the Drain-and-Source Series Resistance of Miniaturized MOSFET’s

Guo, J-C. & Chung, S. S., 1 1月 1994, 於: IEEE Transactions on Electron Devices. 41, 10, p. 1811-1818 8 p.

研究成果: Article › 同行評審

50 引文斯高帕斯（Scopus）

Direct observation of channel-doping-dependent reverse short channel effect using decoupled c-v technique

Guo, J-C., Hsu, C. C. H. & Chung, S. S., 1994, 於: Japanese journal of applied physics. 33, 1, p. 630-634 5 p.

研究成果: Article › 同行評審

3 引文斯高帕斯（Scopus）

Performance and Reliability Evaluation of High Dielectric LDD Spacer on Deep Sub-Micrometer LDD MOSFET

Guo, J-C., Chung, S. S., Lu, C. Y., Lin, P. S. & Hsu, C. C. H., 1 1月 1994, 於: IEEE Transactions on Electron Devices. 41, 7, p. 1239-1248 10 p.

研究成果: Article › 同行評審

4 引文斯高帕斯（Scopus）

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