每年專案
個人檔案
研究專長
奈米元件、高速類比/射頻/非揮發性記憶體元件設計、奈米射頻元件模型、SoC積體電路整合技術
經歷
1998/02~2000/03 世界先進積體電路元件部部經理
2000/03~2003/08 台積電通訊技術部專案經理
2003/08~迄今 國立交通大學電子工程學系/電子研究所教授
教育/學術資格
PhD, 電機工程, 國立陽明交通大學
外部位置
指紋
查看啟用 Jyh-Chyurn Guo 的研究主題。這些主題標籤來自此人的作品。共同形成了獨特的指紋。
- 1 類似的個人檔案
過去五年中的合作和熱門研究領域
國家/地區層面的近期外部共同作業。按一下圓點深入探索詳細資料，或
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毫米波元件與電路協同設計及精實模型研發應用於毫米波高增益與低雜訊放大器以及建構於奈米矽平面與鰭式電晶體技術
1/08/23 → 31/07/24
研究計畫: Other Government Ministry Institute
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毫米波元件與電路協同設計及精實模型研發應用於毫米波高增益與低雜訊放大器以及建構於奈米矽平面與鰭式電晶體技術
1/08/24 → 31/07/25
研究計畫: Other Government Ministry Institute
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毫米波元件與電路協同設計及精實模型研發應用於毫米波高增益與低雜訊放大器以及建構於奈米矽平面與鰭式電晶體技術
1/08/22 → 31/07/23
研究計畫: Other Government Ministry Institute
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新式精簡模型具備佈局相關寄生效應與改善方法應用於低功耗與低雜訊毫米波元件與電路設計
1/08/20 → 31/12/21
研究計畫: Other Government Ministry Institute
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An Area and Energy Efficient All Resistive Neuromorphic-Computing Platform Implemented by a 4-bit-per-cell RG-FinFET Memory
Wu, J. P., Lee, M. Y., Kao, T. C., Li, Y. J., Liu, C. H., Guo, J. C. & Chung, S. S., 2023, 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).研究成果: Conference contribution › 同行評審
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A World First QLC RRAM: Highly Reliable Resistive-Gate Flash with Record 108Endurance and Excellent Retention
Li, M. Y., Lee, J. P., Liu, C. H., Guo, J. C. & Chung, S. S., 2023, 2023 IEEE International Reliability Physics Symposium, IRPS 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (IEEE International Reliability Physics Symposium Proceedings; 卷 2023-March).研究成果: Conference contribution › 同行評審
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The Impact of Nano CMOS Device Scaling on High Frequency Performance and Optimization Principle for fMAXBoost
Wijaya, A. C., Lin, J. M. & Guo, J. C., 2023, 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).研究成果: Conference contribution › 同行評審
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A Built-in Spice Time-domain Variation Model of the BTI-induced Random Trap Fluctuation (RTF) in 14 nm FinFETs
Lin, L. C., Wang, Z. Y., Lee, M. Y., Chang, J. K., Hsieh, E. R., Guo, J. C. & Chung, S. S., 2022, 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022. Institute of Electrical and Electronics Engineers Inc., (2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022).研究成果: Conference contribution › 同行評審
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A New Cascode Design with Enhanced Power gain and Bandwidth for Application in mm-Wave Amplifier
Lin, J. M., Wijaya, A. C. & Guo, J. C., 2022, 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022. Institute of Electrical and Electronics Engineers Inc., (2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022).研究成果: Conference contribution › 同行評審
活動
- 1 Invited talk